152 	val |= (p->regval & (mask >> shift)) << shift;  in access_vm_reg()
169 	p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;  in access_actlr()
220 	vgic_v3_dispatch_sgi(vcpu, p->regval, g1);  in access_gic_sgi()
232 	p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;  in access_gic_sre()
277 		p->regval = (1 << 3);  in trap_oslsr_el1()
289 		p->regval = read_sysreg(dbgauthstatus_el1);  in trap_dbgauthstatus_el1()
326 		vcpu_write_sys_reg(vcpu, p->regval, r->reg);  in trap_debug_regs()
329 		p->regval = vcpu_read_sys_reg(vcpu, r->reg);  in trap_debug_regs()
332 	trace_trap_reg(__func__, r->reg, p->is_write, p->regval);  in trap_debug_regs()
357 	val |= (p->regval & (mask >> shift)) << shift;  in reg_to_dbg()
371 	p->regval = (*dbg_reg & mask) >> shift;  in dbg_to_reg()
668 		val |= p->regval & ARMV8_PMU_PMCR_MASK;  in access_pmcr()
677 		p->regval = val;  in access_pmcr()
690 		__vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;  in access_pmselr()
693 		p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)  in access_pmselr()
715 	p->regval = pmceid;  in access_pmceid()
779 		kvm_pmu_set_counter_value(vcpu, idx, p->regval);  in access_pmu_evcntr()
781 		p->regval = kvm_pmu_get_counter_value(vcpu, idx);  in access_pmu_evcntr()
814 		kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);  in access_pmu_evtyper()
815 		__vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;  in access_pmu_evtyper()
818 		p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;  in access_pmu_evtyper()
834 		val = p->regval & mask;  in access_pmcnten()
846 		p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);  in access_pmcnten()
861 		u64 val = p->regval & mask;  in access_pminten()
870 		p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);  in access_pminten()
887 			__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);  in access_pmovs()
890 			__vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);  in access_pmovs()
892 		p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);  in access_pmovs()
910 	kvm_pmu_software_increment(vcpu, p->regval & mask);  in access_pmswinc()
924 			       p->regval & ARMV8_PMU_USERENR_MASK;  in access_pmuserenr()
926 		p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)  in access_pmuserenr()
1022 		kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);  in access_arch_timer()
1024 		p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);  in access_arch_timer()
1113 	p->regval = read_id_reg(vcpu, r, raz);  in __access_id_reg()
1276 	p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);  in access_ctr()
1286 	p->regval = read_sysreg(clidr_el1);  in access_clidr()
1296 		vcpu_write_sys_reg(vcpu, p->regval, reg);  in access_csselr()
1298 		p->regval = vcpu_read_sys_reg(vcpu, reg);  in access_csselr()
1311 	p->regval = get_ccsidr(csselr);  in access_ccsidr()
1326 		p->regval &= ~GENMASK(27, 3);  in access_ccsidr()
1810 		p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |  in trap_dbgdidr()
2245 		params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;  in kvm_handle_cp_64()
2246 		params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;  in kvm_handle_cp_64()
2257 			vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));  in kvm_handle_cp_64()
2258 			vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));  in kvm_handle_cp_64()
2282 	params.regval = vcpu_get_reg(vcpu, Rt);  in kvm_handle_cp_32()
2291 			vcpu_set_reg(vcpu, Rt, params.regval);  in kvm_handle_cp_32()
2375 	params.regval = vcpu_get_reg(vcpu, Rt);  in kvm_handle_sys_reg()
2380 		vcpu_set_reg(vcpu, Rt, params.regval);  in kvm_handle_sys_reg()