129 static u32 __init find_cap(int bus, int slot, int func, int cap)  in find_cap()  argument
134 	if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &  in find_cap()
138 	pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);  in find_cap()
143 		id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);  in find_cap()
148 		pos = read_pci_config_byte(bus, slot, func,  in find_cap()
155 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)  in read_agp()  argument
164 	pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func);  in read_agp()
165 	apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);  in read_agp()
168 		       bus, slot, func);  in read_agp()
184 	aper_low = read_pci_config(bus, slot, func, 0x10);  in read_agp()
185 	aper_hi = read_pci_config(bus, slot, func, 0x14);  in read_agp()
193 		bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1,  in read_agp()
197 			bus, slot, func, 32 << *order, apsizereg);  in read_agp()
202 		bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1,  in read_agp()
225 	int bus, slot, func;  in search_agp_bridge()  local
228 	for (bus = 0; bus < 256; bus++) {  in search_agp_bridge()
233 				class = read_pci_config(bus, slot, func,  in search_agp_bridge()
242 					cap = find_cap(bus, slot, func,  in search_agp_bridge()
247 					return read_agp(bus, slot, func, cap,  in search_agp_bridge()
252 				type = read_pci_config_byte(bus, slot, func,  in search_agp_bridge()
307 		int bus;  in early_gart_iommu_check()  local
310 		bus = amd_nb_bus_dev_ranges[i].bus;  in early_gart_iommu_check()
315 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in early_gart_iommu_check()
318 			ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);  in early_gart_iommu_check()
322 			aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;  in early_gart_iommu_check()
363 		int bus;  in early_gart_iommu_check()  local
366 		bus = amd_nb_bus_dev_ranges[i].bus;  in early_gart_iommu_check()
371 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in early_gart_iommu_check()
374 			ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);  in early_gart_iommu_check()
376 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);  in early_gart_iommu_check()
407 		int bus;  in gart_iommu_hole_init()  local
411 		bus = amd_nb_bus_dev_ranges[i].bus;  in gart_iommu_hole_init()
416 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in gart_iommu_hole_init()
423 			ctl = read_pci_config(bus, slot, 3,  in gart_iommu_hole_init()
433 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);  in gart_iommu_hole_init()
437 			aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;  in gart_iommu_hole_init()
532 		int bus, dev_base, dev_limit;  in gart_iommu_hole_init()  local
540 		bus = amd_nb_bus_dev_ranges[i].bus;  in gart_iommu_hole_init()
544 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in gart_iommu_hole_init()
547 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);  in gart_iommu_hole_init()
548 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);  in gart_iommu_hole_init()