153 static unsigned int amd_pmc_perf_hw_id(struct kvm_pmc *pmc)  in amd_pmc_perf_hw_id()  argument
156 	u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT;  in amd_pmc_perf_hw_id()
157 	u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;  in amd_pmc_perf_hw_id()
160 	if (guest_cpuid_family(pmc->vcpu) >= 0x17)  in amd_pmc_perf_hw_id()
185 static bool amd_pmc_is_enabled(struct kvm_pmc *pmc)  in amd_pmc_is_enabled()  argument
240 	struct kvm_pmc *pmc;  in amd_msr_idx_to_pmc()  local
242 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);  in amd_msr_idx_to_pmc()
243 	pmc = pmc ? pmc : get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);  in amd_msr_idx_to_pmc()
245 	return pmc;  in amd_msr_idx_to_pmc()
251 	struct kvm_pmc *pmc;  in amd_pmu_get_msr()  local
255 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);  in amd_pmu_get_msr()
256 	if (pmc) {  in amd_pmu_get_msr()
257 		msr_info->data = pmc_read_counter(pmc);  in amd_pmu_get_msr()
261 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);  in amd_pmu_get_msr()
262 	if (pmc) {  in amd_pmu_get_msr()
263 		msr_info->data = pmc->eventsel;  in amd_pmu_get_msr()
273 	struct kvm_pmc *pmc;  in amd_pmu_set_msr()  local
278 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);  in amd_pmu_set_msr()
279 	if (pmc) {  in amd_pmu_set_msr()
280 		pmc->counter += data - pmc_read_counter(pmc);  in amd_pmu_set_msr()
281 		pmc_update_sample_period(pmc);  in amd_pmu_set_msr()
285 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);  in amd_pmu_set_msr()
286 	if (pmc) {  in amd_pmu_set_msr()
288 		if (data != pmc->eventsel)  in amd_pmu_set_msr()
289 			reprogram_gp_counter(pmc, data);  in amd_pmu_set_msr()
337 		struct kvm_pmc *pmc = &pmu->gp_counters[i];  in amd_pmu_reset()  local
339 		pmc_stop_counter(pmc);  in amd_pmu_reset()
340 		pmc->counter = pmc->eventsel = 0;  in amd_pmu_reset()