Lines Matching refs:hpriv
438 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) argument
439 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) argument
440 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) argument
441 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) argument
442 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) argument
577 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
579 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
580 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
582 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
584 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
604 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
606 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
607 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
609 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
611 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
614 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
616 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
617 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
619 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
621 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
622 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
624 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
626 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
628 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
631 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
634 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
922 struct mv_host_priv *hpriv = host->private_data; in mv_host_base() local
923 return hpriv->base; in mv_host_base()
993 struct mv_host_priv *hpriv, in mv_set_edma_ptrs() argument
1023 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) in mv_write_main_irq_mask() argument
1037 writelfl(mask, hpriv->main_irq_mask_addr); in mv_write_main_irq_mask()
1043 struct mv_host_priv *hpriv = host->private_data; in mv_set_main_irq_mask() local
1046 old_mask = hpriv->main_irq_mask; in mv_set_main_irq_mask()
1049 hpriv->main_irq_mask = new_mask; in mv_set_main_irq_mask()
1050 mv_write_main_irq_mask(new_mask, hpriv); in mv_set_main_irq_mask()
1071 struct mv_host_priv *hpriv = ap->host->private_data; in mv_clear_and_enable_port_irqs() local
1085 if (IS_GEN_IIE(hpriv)) in mv_clear_and_enable_port_irqs()
1094 struct mv_host_priv *hpriv = host->private_data; in mv_set_irq_coalescing() local
1095 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_set_irq_coalescing()
1098 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; in mv_set_irq_coalescing()
1117 if (is_dual_hc && !IS_GEN_I(hpriv)) { in mv_set_irq_coalescing()
1174 struct mv_host_priv *hpriv = ap->host->private_data; in mv_start_edma() local
1178 mv_set_edma_ptrs(port_mmio, hpriv, pp); in mv_start_edma()
1365 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv_scr_write() local
1383 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { in mv_scr_write()
1512 struct mv_host_priv *hpriv = ap->host->private_data; in mv_60x1_errata_sata25() local
1516 old = readl(hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1522 writel(new, hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1566 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_enable() local
1570 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) in mv_soc_led_blink_enable()
1572 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_enable()
1581 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_disable() local
1586 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) in mv_soc_led_blink_disable()
1590 for (port = 0; port < hpriv->n_ports; port++) { in mv_soc_led_blink_disable()
1598 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_disable()
1608 struct mv_host_priv *hpriv = ap->host->private_data; in mv_edma_cfg() local
1616 if (IS_GEN_I(hpriv)) in mv_edma_cfg()
1619 else if (IS_GEN_II(hpriv)) { in mv_edma_cfg()
1623 } else if (IS_GEN_IIE(hpriv)) { in mv_edma_cfg()
1645 if (!IS_SOC(hpriv)) in mv_edma_cfg()
1648 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) in mv_edma_cfg()
1652 if (IS_SOC(hpriv)) { in mv_edma_cfg()
1670 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_free_dma_mem() local
1675 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); in mv_port_free_dma_mem()
1679 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); in mv_port_free_dma_mem()
1688 if (tag == 0 || !IS_GEN_I(hpriv)) in mv_port_free_dma_mem()
1689 dma_pool_free(hpriv->sg_tbl_pool, in mv_port_free_dma_mem()
1710 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_start() local
1720 pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); in mv_port_start()
1724 pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); in mv_port_start()
1729 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) in mv_port_start()
1736 if (tag == 0 || !IS_GEN_I(hpriv)) { in mv_port_start()
1737 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, in mv_port_start()
2407 struct mv_host_priv *hpriv = ap->host->private_data; in mv_qc_issue() local
2419 if (IS_GEN_II(hpriv)) in mv_qc_issue()
2646 struct mv_host_priv *hpriv = ap->host->private_data; in mv_err_intr() local
2661 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { in mv_err_intr()
2681 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { in mv_err_intr()
2718 if (IS_GEN_I(hpriv)) { in mv_err_intr()
2806 struct mv_host_priv *hpriv = ap->host->private_data; in mv_process_crpb_entries() local
2823 if (IS_GEN_I(hpriv)) { in mv_process_crpb_entries()
2889 struct mv_host_priv *hpriv = host->private_data; in mv_host_intr() local
2890 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_host_intr()
2897 for (port = 0; port < hpriv->n_ports; port++) { in mv_host_intr()
2932 if ((port + p) >= hpriv->n_ports) in mv_host_intr()
2954 struct mv_host_priv *hpriv = host->private_data; in mv_pci_error() local
2961 err_cause = readl(mmio + hpriv->irq_cause_offset); in mv_pci_error()
2968 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_pci_error()
3009 struct mv_host_priv *hpriv = host->private_data; in mv_interrupt() local
3011 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; in mv_interrupt()
3018 mv_write_main_irq_mask(0, hpriv); in mv_interrupt()
3020 main_irq_cause = readl(hpriv->main_irq_cause_addr); in mv_interrupt()
3021 pending_irqs = main_irq_cause & hpriv->main_irq_mask; in mv_interrupt()
3027 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) in mv_interrupt()
3028 handled = mv_pci_error(host, hpriv->base); in mv_interrupt()
3035 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); in mv_interrupt()
3061 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_read() local
3062 void __iomem *mmio = hpriv->base; in mv5_scr_read()
3075 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_write() local
3076 void __iomem *mmio = hpriv->base; in mv5_scr_write()
3103 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) in mv5_reset_flash() argument
3108 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, in mv5_read_preamp() argument
3116 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ in mv5_read_preamp()
3117 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ in mv5_read_preamp()
3120 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) in mv5_enable_leds() argument
3133 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, in mv5_phy_errata() argument
3139 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); in mv5_phy_errata()
3154 tmp |= hpriv->signal[port].pre; in mv5_phy_errata()
3155 tmp |= hpriv->signal[port].amps; in mv5_phy_errata()
3162 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, in mv5_reset_hc_port() argument
3167 mv_reset_channel(hpriv, mmio, port); in mv5_reset_hc_port()
3186 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, in mv5_reset_one_hc() argument
3204 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, in mv5_reset_hc() argument
3211 mv5_reset_hc_port(hpriv, mmio, in mv5_reset_hc()
3214 mv5_reset_one_hc(hpriv, mmio, hc); in mv5_reset_hc()
3224 struct mv_host_priv *hpriv = host->private_data; in mv_reset_pci_bus() local
3235 ZERO(hpriv->irq_cause_offset); in mv_reset_pci_bus()
3236 ZERO(hpriv->irq_mask_offset); in mv_reset_pci_bus()
3244 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) in mv6_reset_flash() argument
3248 mv5_reset_flash(hpriv, mmio); in mv6_reset_flash()
3265 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, in mv6_reset_hc() argument
3320 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, in mv6_read_preamp() argument
3328 hpriv->signal[idx].amps = 0x7 << 8; in mv6_read_preamp()
3329 hpriv->signal[idx].pre = 0x1 << 5; in mv6_read_preamp()
3336 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv6_read_preamp()
3337 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv6_read_preamp()
3340 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) in mv6_enable_leds() argument
3345 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, in mv6_phy_errata() argument
3350 u32 hp_flags = hpriv->hp_flags; in mv6_phy_errata()
3380 if (IS_SOC(hpriv)) in mv6_phy_errata()
3390 if (IS_GEN_IIE(hpriv)) in mv6_phy_errata()
3408 m2 |= hpriv->signal[port].amps; in mv6_phy_errata()
3409 m2 |= hpriv->signal[port].pre; in mv6_phy_errata()
3413 if (IS_GEN_IIE(hpriv)) { in mv6_phy_errata()
3423 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, in mv_soc_enable_leds() argument
3429 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, in mv_soc_read_preamp() argument
3438 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv_soc_read_preamp()
3439 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv_soc_read_preamp()
3444 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, in mv_soc_reset_hc_port() argument
3449 mv_reset_channel(hpriv, mmio, port); in mv_soc_reset_hc_port()
3469 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, in mv_soc_reset_one_hc() argument
3482 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, in mv_soc_reset_hc() argument
3487 for (port = 0; port < hpriv->n_ports; port++) in mv_soc_reset_hc()
3488 mv_soc_reset_hc_port(hpriv, mmio, port); in mv_soc_reset_hc()
3490 mv_soc_reset_one_hc(hpriv, mmio); in mv_soc_reset_hc()
3495 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, in mv_soc_reset_flash() argument
3506 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, in mv_soc_65n_phy_errata() argument
3544 static bool soc_is_65n(struct mv_host_priv *hpriv) in soc_is_65n() argument
3546 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); in soc_is_65n()
3563 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, in mv_reset_channel() argument
3576 if (!IS_GEN_I(hpriv)) { in mv_reset_channel()
3589 hpriv->ops->phy_errata(hpriv, mmio, port_no); in mv_reset_channel()
3591 if (IS_GEN_I(hpriv)) in mv_reset_channel()
3627 struct mv_host_priv *hpriv = ap->host->private_data; in mv_hardreset() local
3629 void __iomem *mmio = hpriv->base; in mv_hardreset()
3634 mv_reset_channel(hpriv, mmio, ap->port_no); in mv_hardreset()
3650 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { in mv_hardreset()
3671 struct mv_host_priv *hpriv = ap->host->private_data; in mv_eh_thaw() local
3674 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); in mv_eh_thaw()
3735 struct mv_host_priv *hpriv = host->private_data; in mv_in_pcix_mode() local
3736 void __iomem *mmio = hpriv->base; in mv_in_pcix_mode()
3739 if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) in mv_in_pcix_mode()
3749 struct mv_host_priv *hpriv = host->private_data; in mv_pci_cut_through_okay() local
3750 void __iomem *mmio = hpriv->base; in mv_pci_cut_through_okay()
3763 struct mv_host_priv *hpriv = host->private_data; in mv_60x1b2_errata_pci7() local
3764 void __iomem *mmio = hpriv->base; in mv_60x1b2_errata_pci7()
3776 struct mv_host_priv *hpriv = host->private_data; in mv_chip_id() local
3777 u32 hp_flags = hpriv->hp_flags; in mv_chip_id()
3781 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3801 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3821 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3873 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3890 if (soc_is_65n(hpriv)) in mv_chip_id()
3891 hpriv->ops = &mv_soc_65n_ops; in mv_chip_id()
3893 hpriv->ops = &mv_soc_ops; in mv_chip_id()
3903 hpriv->hp_flags = hp_flags; in mv_chip_id()
3905 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; in mv_chip_id()
3906 hpriv->irq_mask_offset = PCIE_IRQ_MASK; in mv_chip_id()
3907 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; in mv_chip_id()
3909 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; in mv_chip_id()
3910 hpriv->irq_mask_offset = PCI_IRQ_MASK; in mv_chip_id()
3911 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; in mv_chip_id()
3930 struct mv_host_priv *hpriv = host->private_data; in mv_init_host() local
3931 void __iomem *mmio = hpriv->base; in mv_init_host()
3933 rc = mv_chip_id(host, hpriv->board_idx); in mv_init_host()
3937 if (IS_SOC(hpriv)) { in mv_init_host()
3938 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3939 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; in mv_init_host()
3941 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3942 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; in mv_init_host()
3946 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); in mv_init_host()
3954 if (hpriv->ops->read_preamp) in mv_init_host()
3955 hpriv->ops->read_preamp(hpriv, port, mmio); in mv_init_host()
3957 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); in mv_init_host()
3961 hpriv->ops->reset_flash(hpriv, mmio); in mv_init_host()
3962 hpriv->ops->reset_bus(host, mmio); in mv_init_host()
3963 hpriv->ops->enable_leds(hpriv, mmio); in mv_init_host()
3984 if (!IS_SOC(hpriv)) { in mv_init_host()
3986 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_init_host()
3989 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); in mv_init_host()
4003 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) in mv_create_dma_pools() argument
4005 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, in mv_create_dma_pools()
4007 if (!hpriv->crqb_pool) in mv_create_dma_pools()
4010 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, in mv_create_dma_pools()
4012 if (!hpriv->crpb_pool) in mv_create_dma_pools()
4015 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, in mv_create_dma_pools()
4017 if (!hpriv->sg_tbl_pool) in mv_create_dma_pools()
4023 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, in mv_conf_mbus_windows() argument
4029 writel(0, hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4030 writel(0, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4039 hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4040 writel(cs->base, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4059 struct mv_host_priv *hpriv; in mv_platform_probe() local
4110 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_platform_probe()
4112 if (!host || !hpriv) in mv_platform_probe()
4114 hpriv->port_clks = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4117 if (!hpriv->port_clks) in mv_platform_probe()
4119 hpriv->port_phys = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4122 if (!hpriv->port_phys) in mv_platform_probe()
4124 host->private_data = hpriv; in mv_platform_probe()
4125 hpriv->board_idx = chip_soc; in mv_platform_probe()
4128 hpriv->base = devm_ioremap(&pdev->dev, res->start, in mv_platform_probe()
4130 if (!hpriv->base) in mv_platform_probe()
4133 hpriv->base -= SATAHC0_REG_BASE; in mv_platform_probe()
4135 hpriv->clk = clk_get(&pdev->dev, NULL); in mv_platform_probe()
4136 if (IS_ERR(hpriv->clk)) in mv_platform_probe()
4139 clk_prepare_enable(hpriv->clk); in mv_platform_probe()
4144 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); in mv_platform_probe()
4145 if (!IS_ERR(hpriv->port_clks[port])) in mv_platform_probe()
4146 clk_prepare_enable(hpriv->port_clks[port]); in mv_platform_probe()
4149 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, in mv_platform_probe()
4151 if (IS_ERR(hpriv->port_phys[port])) { in mv_platform_probe()
4152 rc = PTR_ERR(hpriv->port_phys[port]); in mv_platform_probe()
4153 hpriv->port_phys[port] = NULL; in mv_platform_probe()
4158 hpriv->n_ports = port; in mv_platform_probe()
4161 phy_power_on(hpriv->port_phys[port]); in mv_platform_probe()
4165 hpriv->n_ports = n_ports; in mv_platform_probe()
4172 mv_conf_mbus_windows(hpriv, dram); in mv_platform_probe()
4174 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_platform_probe()
4185 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; in mv_platform_probe()
4200 if (!IS_ERR(hpriv->clk)) { in mv_platform_probe()
4201 clk_disable_unprepare(hpriv->clk); in mv_platform_probe()
4202 clk_put(hpriv->clk); in mv_platform_probe()
4204 for (port = 0; port < hpriv->n_ports; port++) { in mv_platform_probe()
4205 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_probe()
4206 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_probe()
4207 clk_put(hpriv->port_clks[port]); in mv_platform_probe()
4209 phy_power_off(hpriv->port_phys[port]); in mv_platform_probe()
4226 struct mv_host_priv *hpriv = host->private_data; in mv_platform_remove() local
4230 if (!IS_ERR(hpriv->clk)) { in mv_platform_remove()
4231 clk_disable_unprepare(hpriv->clk); in mv_platform_remove()
4232 clk_put(hpriv->clk); in mv_platform_remove()
4235 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_remove()
4236 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_remove()
4237 clk_put(hpriv->port_clks[port]); in mv_platform_remove()
4239 phy_power_off(hpriv->port_phys[port]); in mv_platform_remove()
4261 struct mv_host_priv *hpriv = host->private_data; in mv_platform_resume() local
4268 mv_conf_mbus_windows(hpriv, dram); in mv_platform_resume()
4339 struct mv_host_priv *hpriv = host->private_data; in mv_print_info() local
4354 if (IS_GEN_I(hpriv)) in mv_print_info()
4356 else if (IS_GEN_II(hpriv)) in mv_print_info()
4358 else if (IS_GEN_IIE(hpriv)) in mv_print_info()
4365 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); in mv_print_info()
4382 struct mv_host_priv *hpriv; in mv_pci_init_one() local
4391 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_pci_init_one()
4392 if (!host || !hpriv) in mv_pci_init_one()
4394 host->private_data = hpriv; in mv_pci_init_one()
4395 hpriv->n_ports = n_ports; in mv_pci_init_one()
4396 hpriv->board_idx = board_idx; in mv_pci_init_one()
4409 hpriv->base = host->iomap[MV_PRIMARY_BAR]; in mv_pci_init_one()
4417 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_pci_init_one()
4423 void __iomem *port_mmio = mv_port_base(hpriv->base, port); in mv_pci_init_one()
4424 unsigned int offset = port_mmio - hpriv->base; in mv_pci_init_one()
4437 hpriv->hp_flags |= MV_HP_FLAG_MSI; in mv_pci_init_one()
4445 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); in mv_pci_init_one()