192 	u8 __iomem *mmio_base = qs_mmio_base(ap->host);  in qs_freeze()  local
194 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */  in qs_freeze()
200 	u8 __iomem *mmio_base = qs_mmio_base(ap->host);  in qs_thaw()  local
203 	writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */  in qs_thaw()
361 	u8 __iomem *mmio_base = qs_mmio_base(host);  in qs_intr_pkt()  local
364 		u32 sff0 = readl(mmio_base + QS_HST_SFF);  in qs_intr_pkt()
365 		u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);  in qs_intr_pkt()
471 	void __iomem *mmio_base = qs_mmio_base(ap->host);  in qs_port_start()  local
472 	void __iomem *chan = mmio_base + (ap->port_no * 0x4000);  in qs_port_start()
493 	void __iomem *mmio_base = qs_mmio_base(host);  in qs_host_stop()  local
495 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */  in qs_host_stop()
496 	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */  in qs_host_stop()
501 	void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];  in qs_host_init()  local
504 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */  in qs_host_init()
505 	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */  in qs_host_init()
509 		u8 __iomem *chan = mmio_base + (port_no * 0x4000);  in qs_host_init()
514 	writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */  in qs_host_init()
517 		u8 __iomem *chan = mmio_base + (port_no * 0x4000);  in qs_host_init()
526 	writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */  in qs_host_init()
539 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)  in qs_set_dma_masks()  argument
541 	u32 bus_info = readl(mmio_base + QS_HID_HPHY);  in qs_set_dma_masks()