60 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)  in clk_pllv3_wait_lock()  argument
62 	u32 val = readl_relaxed(pll->base) & pll->power_bit;  in clk_pllv3_wait_lock()
65 	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))  in clk_pllv3_wait_lock()
68 	return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,  in clk_pllv3_wait_lock()
74 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_prepare()  local
77 	val = readl_relaxed(pll->base);  in clk_pllv3_prepare()
78 	if (pll->powerup_set)  in clk_pllv3_prepare()
79 		val |= pll->power_bit;  in clk_pllv3_prepare()
81 		val &= ~pll->power_bit;  in clk_pllv3_prepare()
82 	writel_relaxed(val, pll->base);  in clk_pllv3_prepare()
84 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_prepare()
89 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_unprepare()  local
92 	val = readl_relaxed(pll->base);  in clk_pllv3_unprepare()
93 	if (pll->powerup_set)  in clk_pllv3_unprepare()
94 		val &= ~pll->power_bit;  in clk_pllv3_unprepare()
96 		val |= pll->power_bit;  in clk_pllv3_unprepare()
97 	writel_relaxed(val, pll->base);  in clk_pllv3_unprepare()
102 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_is_prepared()  local
104 	if (readl_relaxed(pll->base) & BM_PLL_LOCK)  in clk_pllv3_is_prepared()
113 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_recalc_rate()  local
114 	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;  in clk_pllv3_recalc_rate()
131 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_set_rate()  local
141 	val = readl_relaxed(pll->base);  in clk_pllv3_set_rate()
142 	val &= ~(pll->div_mask << pll->div_shift);  in clk_pllv3_set_rate()
143 	val |= (div << pll->div_shift);  in clk_pllv3_set_rate()
144 	writel_relaxed(val, pll->base);  in clk_pllv3_set_rate()
146 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_set_rate()
161 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_sys_recalc_rate()  local
162 	u32 div = readl_relaxed(pll->base) & pll->div_mask;  in clk_pllv3_sys_recalc_rate()
187 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_sys_set_rate()  local
196 	val = readl_relaxed(pll->base);  in clk_pllv3_sys_set_rate()
197 	val &= ~pll->div_mask;  in clk_pllv3_sys_set_rate()
199 	writel_relaxed(val, pll->base);  in clk_pllv3_sys_set_rate()
201 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_sys_set_rate()
216 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_av_recalc_rate()  local
217 	u32 mfn = readl_relaxed(pll->base + pll->num_offset);  in clk_pllv3_av_recalc_rate()
218 	u32 mfd = readl_relaxed(pll->base + pll->denom_offset);  in clk_pllv3_av_recalc_rate()
219 	u32 div = readl_relaxed(pll->base) & pll->div_mask;  in clk_pllv3_av_recalc_rate()
263 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_av_set_rate()  local
283 	val = readl_relaxed(pll->base);  in clk_pllv3_av_set_rate()
284 	val &= ~pll->div_mask;  in clk_pllv3_av_set_rate()
286 	writel_relaxed(val, pll->base);  in clk_pllv3_av_set_rate()
287 	writel_relaxed(mfn, pll->base + pll->num_offset);  in clk_pllv3_av_set_rate()
288 	writel_relaxed(mfd, pll->base + pll->denom_offset);  in clk_pllv3_av_set_rate()
290 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_av_set_rate()
347 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_vf610_recalc_rate()  local
350 	mf.mfn = readl_relaxed(pll->base + pll->num_offset);  in clk_pllv3_vf610_recalc_rate()
351 	mf.mfd = readl_relaxed(pll->base + pll->denom_offset);  in clk_pllv3_vf610_recalc_rate()
352 	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;  in clk_pllv3_vf610_recalc_rate()
368 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_vf610_set_rate()  local
373 	val = readl_relaxed(pll->base);  in clk_pllv3_vf610_set_rate()
375 		val &= ~pll->div_mask;	/* clear bit for mfi=20 */  in clk_pllv3_vf610_set_rate()
377 		val |= pll->div_mask;	/* set bit for mfi=22 */  in clk_pllv3_vf610_set_rate()
378 	writel_relaxed(val, pll->base);  in clk_pllv3_vf610_set_rate()
380 	writel_relaxed(mf.mfn, pll->base + pll->num_offset);  in clk_pllv3_vf610_set_rate()
381 	writel_relaxed(mf.mfd, pll->base + pll->denom_offset);  in clk_pllv3_vf610_set_rate()
383 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_vf610_set_rate()
398 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_enet_recalc_rate()  local
400 	return pll->ref_clock;  in clk_pllv3_enet_recalc_rate()
414 	struct clk_pllv3 *pll;  in imx_clk_hw_pllv3()  local
420 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in imx_clk_hw_pllv3()
421 	if (!pll)  in imx_clk_hw_pllv3()
424 	pll->power_bit = BM_PLL_POWER;  in imx_clk_hw_pllv3()
425 	pll->num_offset = PLL_NUM_OFFSET;  in imx_clk_hw_pllv3()
426 	pll->denom_offset = PLL_DENOM_OFFSET;  in imx_clk_hw_pllv3()
434 		pll->num_offset = PLL_VF610_NUM_OFFSET;  in imx_clk_hw_pllv3()
435 		pll->denom_offset = PLL_VF610_DENOM_OFFSET;  in imx_clk_hw_pllv3()
438 		pll->div_shift = 1;  in imx_clk_hw_pllv3()
442 		pll->powerup_set = true;  in imx_clk_hw_pllv3()
445 		pll->num_offset = PLL_IMX7_NUM_OFFSET;  in imx_clk_hw_pllv3()
446 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;  in imx_clk_hw_pllv3()
452 		pll->power_bit = IMX7_ENET_PLL_POWER;  in imx_clk_hw_pllv3()
453 		pll->ref_clock = 1000000000;  in imx_clk_hw_pllv3()
457 		pll->ref_clock = 500000000;  in imx_clk_hw_pllv3()
461 		pll->power_bit = IMX7_DDR_PLL_POWER;  in imx_clk_hw_pllv3()
462 		pll->num_offset = PLL_IMX7_NUM_OFFSET;  in imx_clk_hw_pllv3()
463 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;  in imx_clk_hw_pllv3()
469 	pll->base = base;  in imx_clk_hw_pllv3()
470 	pll->div_mask = div_mask;  in imx_clk_hw_pllv3()
478 	pll->hw.init = &init;  in imx_clk_hw_pllv3()
479 	hw = &pll->hw;  in imx_clk_hw_pllv3()
483 		kfree(pll);  in imx_clk_hw_pllv3()