Lines Matching refs:name
65 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ argument
66 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
68 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
70 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
73 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ argument
74 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
76 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
77 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
79 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
80 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
82 #define imx_clk_fixed(name, rate) \ argument
83 to_clk(imx_clk_hw_fixed(name, rate))
85 #define imx_clk_fixed_factor(name, parent, mult, div) \ argument
86 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
88 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
89 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
91 #define imx_clk_divider2(name, parent, reg, shift, width) \ argument
92 to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
94 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ argument
95 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
97 #define imx_clk_gate(name, parent, reg, shift) \ argument
98 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
100 #define imx_clk_gate_dis(name, parent, reg, shift) \ argument
101 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
103 #define imx_clk_gate2(name, parent, reg, shift) \ argument
104 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
106 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ argument
107 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
109 #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \ argument
110 to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))
112 #define imx_clk_gate3(name, parent, reg, shift) \ argument
113 to_clk(imx_clk_hw_gate3(name, parent, reg, shift))
115 #define imx_clk_gate4(name, parent, reg, shift) \ argument
116 to_clk(imx_clk_hw_gate4(name, parent, reg, shift))
118 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
119 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
121 #define imx_clk_pllv1(type, name, parent, base) \ argument
122 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
124 #define imx_clk_pllv2(name, parent, base) \ argument
125 to_clk(imx_clk_hw_pllv2(name, parent, base))
127 #define imx_clk_frac_pll(name, parent_name, base) \ argument
128 to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
130 #define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\ argument
132 to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
135 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
138 #define imx_clk_pll14xx(name, parent_name, base, pll_clk) \ argument
139 to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
141 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
145 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
148 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
151 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
154 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
174 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
194 struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
197 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
204 const char *name, unsigned long rate);
207 const char *name, unsigned long rate);
210 const char *name);
212 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
215 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
218 struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
221 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
225 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
229 struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
235 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
239 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
250 static inline struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name, in imx_clk_hw_pll14xx() argument
254 return imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk); in imx_clk_hw_pll14xx()
257 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) in imx_clk_hw_fixed() argument
259 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); in imx_clk_hw_fixed()
262 static inline struct clk_hw *imx_clk_hw_mux_ldb(const char *name, void __iomem *reg, in imx_clk_hw_mux_ldb() argument
266 return clk_hw_register_mux(NULL, name, parents, num_parents, in imx_clk_hw_mux_ldb()
271 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name, in imx_clk_hw_fixed_factor() argument
274 return clk_hw_register_fixed_factor(NULL, name, parent, in imx_clk_hw_fixed_factor()
278 static inline struct clk_hw *imx_clk_hw_divider(const char *name, in imx_clk_hw_divider() argument
283 return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, in imx_clk_hw_divider()
287 static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name, in imx_clk_hw_divider_flags() argument
292 return clk_hw_register_divider(NULL, name, parent, flags, in imx_clk_hw_divider_flags()
296 static inline struct clk_hw *imx_clk_hw_divider2(const char *name, const char *parent, in imx_clk_hw_divider2() argument
299 return clk_hw_register_divider(NULL, name, parent, in imx_clk_hw_divider2()
304 static inline struct clk *imx_clk_divider2_flags(const char *name, in imx_clk_divider2_flags() argument
308 return clk_register_divider(NULL, name, parent, in imx_clk_divider2_flags()
313 static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent, in imx_clk_hw_gate_flags() argument
316 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, in imx_clk_hw_gate_flags()
320 static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent, in imx_clk_hw_gate() argument
323 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_hw_gate()
327 static inline struct clk_hw *imx_dev_clk_hw_gate(struct device *dev, const char *name, in imx_dev_clk_hw_gate() argument
330 return clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg, in imx_dev_clk_hw_gate()
334 static inline struct clk_hw *imx_clk_hw_gate_dis(const char *name, const char *parent, in imx_clk_hw_gate_dis() argument
337 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_hw_gate_dis()
341 static inline struct clk_hw *imx_clk_hw_gate_dis_flags(const char *name, const char *parent, in imx_clk_hw_gate_dis_flags() argument
344 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, in imx_clk_hw_gate_dis_flags()
348 static inline struct clk_hw *imx_clk_hw_gate2(const char *name, const char *parent, in imx_clk_hw_gate2() argument
351 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_hw_gate2()
355 static inline struct clk_hw *imx_clk_hw_gate2_flags(const char *name, const char *parent, in imx_clk_hw_gate2_flags() argument
358 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, in imx_clk_hw_gate2_flags()
362 static inline struct clk_hw *imx_clk_hw_gate2_shared(const char *name, in imx_clk_hw_gate2_shared() argument
366 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_hw_gate2_shared()
370 static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name, in imx_clk_hw_gate2_shared2() argument
374 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | in imx_clk_hw_gate2_shared2()
380 const char *name, const char *parent, in imx_dev_clk_hw_gate_shared() argument
384 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | in imx_dev_clk_hw_gate_shared()
389 static inline struct clk *imx_clk_gate2_cgr(const char *name, in imx_clk_gate2_cgr() argument
392 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2_cgr()
396 static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent, in imx_clk_hw_gate3() argument
399 return clk_hw_register_gate(NULL, name, parent, in imx_clk_hw_gate3()
404 static inline struct clk_hw *imx_clk_hw_gate3_flags(const char *name, in imx_clk_hw_gate3_flags() argument
408 return clk_hw_register_gate(NULL, name, parent, in imx_clk_hw_gate3_flags()
413 #define imx_clk_gate3_flags(name, parent, reg, shift, flags) \ argument
414 to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags))
416 static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *parent, in imx_clk_hw_gate4() argument
419 return clk_hw_register_gate2(NULL, name, parent, in imx_clk_hw_gate4()
424 static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name, in imx_clk_hw_gate4_flags() argument
428 return clk_hw_register_gate2(NULL, name, parent, in imx_clk_hw_gate4_flags()
433 #define imx_clk_gate4_flags(name, parent, reg, shift, flags) \ argument
434 to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags))
436 static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg, in imx_clk_hw_mux() argument
440 return clk_hw_register_mux(NULL, name, parents, num_parents, in imx_clk_hw_mux()
446 const char *name, void __iomem *reg, u8 shift, in imx_dev_clk_hw_mux() argument
449 return clk_hw_register_mux(dev, name, parents, num_parents, in imx_dev_clk_hw_mux()
454 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, in imx_clk_mux2() argument
458 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux2()
463 static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg, in imx_clk_hw_mux2() argument
468 return clk_hw_register_mux(NULL, name, parents, num_parents, in imx_clk_hw_mux2()
474 static inline struct clk *imx_clk_mux_flags(const char *name, in imx_clk_mux_flags() argument
479 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux_flags()
484 static inline struct clk_hw *imx_clk_hw_mux2_flags(const char *name, in imx_clk_hw_mux2_flags() argument
489 return clk_hw_register_mux(NULL, name, parents, num_parents, in imx_clk_hw_mux2_flags()
494 static inline struct clk *imx_clk_mux2_flags(const char *name, in imx_clk_mux2_flags() argument
499 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux2_flags()
504 static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name, in imx_clk_hw_mux_flags() argument
511 return clk_hw_register_mux(NULL, name, parents, num_parents, in imx_clk_hw_mux_flags()
517 const char *name, in imx_dev_clk_hw_mux_flags() argument
524 return clk_hw_register_mux(dev, name, parents, num_parents, in imx_dev_clk_hw_mux_flags()
529 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
537 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
544 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \ argument
545 imx8m_clk_hw_composite_flags(name, parent_names, \
550 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \ argument
551 imx8m_clk_hw_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \
555 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \ argument
556 imx8m_clk_hw_composite_flags(name, parent_names, \
561 #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \ argument
563 to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
566 #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \ argument
567 imx8m_clk_hw_composite_flags(name, parent_names, \
571 #define __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, flags) \ argument
572 imx8m_clk_hw_composite_flags(name, parent_names, \
576 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \ argument
577 __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, 0)
579 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \ argument
580 __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, CLK_IS_CRITICAL)
582 #define __imx8m_clk_composite(name, parent_names, reg, flags) \ argument
583 to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))
585 #define imx8m_clk_hw_composite(name, parent_names, reg) \ argument
586 __imx8m_clk_hw_composite(name, parent_names, reg, 0)
588 #define imx8m_clk_composite(name, parent_names, reg) \ argument
589 __imx8m_clk_composite(name, parent_names, reg, 0)
591 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ argument
592 __imx8m_clk_hw_composite(name, parent_names, reg, CLK_IS_CRITICAL)
594 #define imx8m_clk_composite_critical(name, parent_names, reg) \ argument
595 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
597 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,