Lines Matching refs:MUX

363 	MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
365 	MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
367 	MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
369 	MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
371 	MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
373 	MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
375 	MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
377 	MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
380 	MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
382 	MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
384 	MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
387 	MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
389 	MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
391 	MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
393 	MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
395 	MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
397 	MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
399 	MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
401 	MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
404 	MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
406 	MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
408 	MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
410 	MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
412 	MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
414 	MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
416 	MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
419 	MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
421 	MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
423 	MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
425 	MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
427 	MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
429 	MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
431 	MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
433 	MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
455 	MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
457 	MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
459 	MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
461 	MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
463 	MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,