Lines Matching refs:MUX
209 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
213 MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
217 MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
221 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
225 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
229 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
233 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
237 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
241 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
245 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
249 MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT,
253 MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT,
257 MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT,
261 MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT,
269 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
548 MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT,
556 MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT,