Lines Matching refs:ch
242 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) in sh_cmt_read_cmstr() argument
244 if (ch->iostart) in sh_cmt_read_cmstr()
245 return ch->cmt->info->read_control(ch->iostart, 0); in sh_cmt_read_cmstr()
247 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); in sh_cmt_read_cmstr()
250 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmstr() argument
252 u32 old_value = sh_cmt_read_cmstr(ch); in sh_cmt_write_cmstr()
255 if (ch->iostart) { in sh_cmt_write_cmstr()
256 ch->cmt->info->write_control(ch->iostart, 0, value); in sh_cmt_write_cmstr()
257 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
259 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); in sh_cmt_write_cmstr()
260 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
265 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) in sh_cmt_read_cmcsr() argument
267 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); in sh_cmt_read_cmcsr()
270 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmcsr() argument
272 u32 old_value = sh_cmt_read_cmcsr(ch); in sh_cmt_write_cmcsr()
275 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); in sh_cmt_write_cmcsr()
276 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmcsr()
280 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) in sh_cmt_read_cmcnt() argument
282 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); in sh_cmt_read_cmcnt()
285 static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmcnt() argument
288 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2); in sh_cmt_write_cmcnt()
291 if (ch->cmt->info->model > SH_CMT_16BIT) { in sh_cmt_write_cmcnt()
294 1, cmcnt_delay, false, ch); in sh_cmt_write_cmcnt()
299 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); in sh_cmt_write_cmcnt()
304 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmcor() argument
306 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR); in sh_cmt_write_cmcor()
309 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); in sh_cmt_write_cmcor()
310 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmcor()
314 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) in sh_cmt_get_counter() argument
319 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
324 v1 = sh_cmt_read_cmcnt(ch); in sh_cmt_get_counter()
325 v2 = sh_cmt_read_cmcnt(ch); in sh_cmt_get_counter()
326 v3 = sh_cmt_read_cmcnt(ch); in sh_cmt_get_counter()
327 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
335 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) in sh_cmt_start_stop_ch() argument
341 raw_spin_lock_irqsave(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
342 value = sh_cmt_read_cmstr(ch); in sh_cmt_start_stop_ch()
345 value |= 1 << ch->timer_bit; in sh_cmt_start_stop_ch()
347 value &= ~(1 << ch->timer_bit); in sh_cmt_start_stop_ch()
349 sh_cmt_write_cmstr(ch, value); in sh_cmt_start_stop_ch()
350 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
353 static int sh_cmt_enable(struct sh_cmt_channel *ch) in sh_cmt_enable() argument
357 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); in sh_cmt_enable()
360 ret = clk_enable(ch->cmt->clk); in sh_cmt_enable()
362 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", in sh_cmt_enable()
363 ch->index); in sh_cmt_enable()
368 sh_cmt_start_stop_ch(ch, 0); in sh_cmt_enable()
371 if (ch->cmt->info->width == 16) { in sh_cmt_enable()
372 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | in sh_cmt_enable()
375 u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ? in sh_cmt_enable()
377 sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM | in sh_cmt_enable()
382 sh_cmt_write_cmcor(ch, 0xffffffff); in sh_cmt_enable()
383 ret = sh_cmt_write_cmcnt(ch, 0); in sh_cmt_enable()
385 if (ret || sh_cmt_read_cmcnt(ch)) { in sh_cmt_enable()
386 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", in sh_cmt_enable()
387 ch->index); in sh_cmt_enable()
393 sh_cmt_start_stop_ch(ch, 1); in sh_cmt_enable()
397 clk_disable(ch->cmt->clk); in sh_cmt_enable()
403 static void sh_cmt_disable(struct sh_cmt_channel *ch) in sh_cmt_disable() argument
406 sh_cmt_start_stop_ch(ch, 0); in sh_cmt_disable()
409 sh_cmt_write_cmcsr(ch, 0); in sh_cmt_disable()
412 clk_disable(ch->cmt->clk); in sh_cmt_disable()
414 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); in sh_cmt_disable()
424 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, in sh_cmt_clock_event_program_verify() argument
427 u32 value = ch->next_match_value; in sh_cmt_clock_event_program_verify()
433 now = sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clock_event_program_verify()
434 ch->flags |= FLAG_REPROGRAM; /* force reprogram */ in sh_cmt_clock_event_program_verify()
441 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
453 if (new_match > ch->max_match_value) in sh_cmt_clock_event_program_verify()
454 new_match = ch->max_match_value; in sh_cmt_clock_event_program_verify()
456 sh_cmt_write_cmcor(ch, new_match); in sh_cmt_clock_event_program_verify()
458 now = sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clock_event_program_verify()
459 if (has_wrapped && (new_match > ch->match_value)) { in sh_cmt_clock_event_program_verify()
466 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
477 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
488 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
504 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", in sh_cmt_clock_event_program_verify()
505 ch->index); in sh_cmt_clock_event_program_verify()
510 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) in __sh_cmt_set_next() argument
512 if (delta > ch->max_match_value) in __sh_cmt_set_next()
513 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", in __sh_cmt_set_next()
514 ch->index); in __sh_cmt_set_next()
516 ch->next_match_value = delta; in __sh_cmt_set_next()
517 sh_cmt_clock_event_program_verify(ch, 0); in __sh_cmt_set_next()
520 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) in sh_cmt_set_next() argument
524 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_set_next()
525 __sh_cmt_set_next(ch, delta); in sh_cmt_set_next()
526 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_set_next()
531 struct sh_cmt_channel *ch = dev_id; in sh_cmt_interrupt() local
534 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & in sh_cmt_interrupt()
535 ch->cmt->info->clear_bits); in sh_cmt_interrupt()
541 if (ch->flags & FLAG_CLOCKSOURCE) in sh_cmt_interrupt()
542 ch->total_cycles += ch->match_value + 1; in sh_cmt_interrupt()
544 if (!(ch->flags & FLAG_REPROGRAM)) in sh_cmt_interrupt()
545 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
547 ch->flags |= FLAG_IRQCONTEXT; in sh_cmt_interrupt()
549 if (ch->flags & FLAG_CLOCKEVENT) { in sh_cmt_interrupt()
550 if (!(ch->flags & FLAG_SKIPEVENT)) { in sh_cmt_interrupt()
551 if (clockevent_state_oneshot(&ch->ced)) { in sh_cmt_interrupt()
552 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
553 ch->flags |= FLAG_REPROGRAM; in sh_cmt_interrupt()
556 ch->ced.event_handler(&ch->ced); in sh_cmt_interrupt()
560 ch->flags &= ~FLAG_SKIPEVENT; in sh_cmt_interrupt()
562 if (ch->flags & FLAG_REPROGRAM) { in sh_cmt_interrupt()
563 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
564 sh_cmt_clock_event_program_verify(ch, 1); in sh_cmt_interrupt()
566 if (ch->flags & FLAG_CLOCKEVENT) in sh_cmt_interrupt()
567 if ((clockevent_state_shutdown(&ch->ced)) in sh_cmt_interrupt()
568 || (ch->match_value == ch->next_match_value)) in sh_cmt_interrupt()
569 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
572 ch->flags &= ~FLAG_IRQCONTEXT; in sh_cmt_interrupt()
577 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) in sh_cmt_start() argument
583 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_start()
585 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_start()
587 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { in sh_cmt_start()
589 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_start()
590 ret = sh_cmt_enable(ch); in sh_cmt_start()
595 ch->flags |= flag; in sh_cmt_start()
598 if (ch->cmt->num_channels == 1 && in sh_cmt_start()
599 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) in sh_cmt_start()
600 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_start()
602 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_start()
607 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) in sh_cmt_stop() argument
612 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_stop()
614 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); in sh_cmt_stop()
615 ch->flags &= ~flag; in sh_cmt_stop()
617 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { in sh_cmt_stop()
618 sh_cmt_disable(ch); in sh_cmt_stop()
620 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_stop()
624 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) in sh_cmt_stop()
625 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_stop()
627 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_stop()
630 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_stop()
640 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_read() local
643 if (ch->cmt->num_channels == 1) { in sh_cmt_clocksource_read()
648 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_clocksource_read()
649 value = ch->total_cycles; in sh_cmt_clocksource_read()
650 raw = sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clocksource_read()
653 raw += ch->match_value + 1; in sh_cmt_clocksource_read()
654 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_clocksource_read()
659 return sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clocksource_read()
665 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_enable() local
667 WARN_ON(ch->cs_enabled); in sh_cmt_clocksource_enable()
669 ch->total_cycles = 0; in sh_cmt_clocksource_enable()
671 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_enable()
673 ch->cs_enabled = true; in sh_cmt_clocksource_enable()
680 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_disable() local
682 WARN_ON(!ch->cs_enabled); in sh_cmt_clocksource_disable()
684 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_disable()
685 ch->cs_enabled = false; in sh_cmt_clocksource_disable()
690 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_suspend() local
692 if (!ch->cs_enabled) in sh_cmt_clocksource_suspend()
695 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_suspend()
696 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); in sh_cmt_clocksource_suspend()
701 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_resume() local
703 if (!ch->cs_enabled) in sh_cmt_clocksource_resume()
706 dev_pm_genpd_resume(&ch->cmt->pdev->dev); in sh_cmt_clocksource_resume()
707 sh_cmt_start(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_resume()
710 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, in sh_cmt_register_clocksource() argument
713 struct clocksource *cs = &ch->cs; in sh_cmt_register_clocksource()
722 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); in sh_cmt_register_clocksource()
725 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", in sh_cmt_register_clocksource()
726 ch->index); in sh_cmt_register_clocksource()
728 clocksource_register_hz(cs, ch->cmt->rate); in sh_cmt_register_clocksource()
737 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) in sh_cmt_clock_event_start() argument
739 sh_cmt_start(ch, FLAG_CLOCKEVENT); in sh_cmt_clock_event_start()
742 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); in sh_cmt_clock_event_start()
744 sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_clock_event_start()
749 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_shutdown() local
751 sh_cmt_stop(ch, FLAG_CLOCKEVENT); in sh_cmt_clock_event_shutdown()
758 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_set_state() local
762 sh_cmt_stop(ch, FLAG_CLOCKEVENT); in sh_cmt_clock_event_set_state()
764 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", in sh_cmt_clock_event_set_state()
765 ch->index, periodic ? "periodic" : "oneshot"); in sh_cmt_clock_event_set_state()
766 sh_cmt_clock_event_start(ch, periodic); in sh_cmt_clock_event_set_state()
783 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_next() local
786 if (likely(ch->flags & FLAG_IRQCONTEXT)) in sh_cmt_clock_event_next()
787 ch->next_match_value = delta - 1; in sh_cmt_clock_event_next()
789 sh_cmt_set_next(ch, delta - 1); in sh_cmt_clock_event_next()
796 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_suspend() local
798 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); in sh_cmt_clock_event_suspend()
799 clk_unprepare(ch->cmt->clk); in sh_cmt_clock_event_suspend()
804 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_resume() local
806 clk_prepare(ch->cmt->clk); in sh_cmt_clock_event_resume()
807 dev_pm_genpd_resume(&ch->cmt->pdev->dev); in sh_cmt_clock_event_resume()
810 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, in sh_cmt_register_clockevent() argument
813 struct clock_event_device *ced = &ch->ced; in sh_cmt_register_clockevent()
817 irq = platform_get_irq(ch->cmt->pdev, ch->index); in sh_cmt_register_clockevent()
823 dev_name(&ch->cmt->pdev->dev), ch); in sh_cmt_register_clockevent()
825 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", in sh_cmt_register_clockevent()
826 ch->index, irq); in sh_cmt_register_clockevent()
844 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); in sh_cmt_register_clockevent()
845 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); in sh_cmt_register_clockevent()
846 ced->max_delta_ticks = ch->max_match_value; in sh_cmt_register_clockevent()
850 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", in sh_cmt_register_clockevent()
851 ch->index); in sh_cmt_register_clockevent()
857 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, in sh_cmt_register() argument
863 ch->cmt->has_clockevent = true; in sh_cmt_register()
864 ret = sh_cmt_register_clockevent(ch, name); in sh_cmt_register()
870 ch->cmt->has_clocksource = true; in sh_cmt_register()
871 sh_cmt_register_clocksource(ch, name); in sh_cmt_register()
877 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, in sh_cmt_setup_channel() argument
888 ch->cmt = cmt; in sh_cmt_setup_channel()
889 ch->index = index; in sh_cmt_setup_channel()
890 ch->hwidx = hwidx; in sh_cmt_setup_channel()
891 ch->timer_bit = hwidx; in sh_cmt_setup_channel()
900 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; in sh_cmt_setup_channel()
904 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; in sh_cmt_setup_channel()
908 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; in sh_cmt_setup_channel()
909 ch->ioctrl = ch->iostart + 0x10; in sh_cmt_setup_channel()
910 ch->timer_bit = 0; in sh_cmt_setup_channel()
919 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) in sh_cmt_setup_channel()
920 ch->max_match_value = ~0; in sh_cmt_setup_channel()
922 ch->max_match_value = (1 << cmt->info->width) - 1; in sh_cmt_setup_channel()
924 ch->match_value = ch->max_match_value; in sh_cmt_setup_channel()
925 raw_spin_lock_init(&ch->lock); in sh_cmt_setup_channel()
927 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), in sh_cmt_setup_channel()
931 ch->index); in sh_cmt_setup_channel()
934 ch->cs_enabled = false; in sh_cmt_setup_channel()