Lines Matching refs:u32
101 static inline void wr_reg32(void __iomem *reg, u32 data) in wr_reg32()
109 static inline u32 rd_reg32(void __iomem *reg) in rd_reg32()
117 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) in clrsetbits_32()
146 iowrite32(data >> 32, (u32 __iomem *)(reg)); in wr_reg64()
147 iowrite32(data, (u32 __iomem *)(reg) + 1); in wr_reg64()
160 u32 low, high; in rd_reg64()
163 low = ioread32(reg + sizeof(u32)); in rd_reg64()
221 u32 *jrstatus) in jr_outentry_get()
224 if (caam_ptr_sz == sizeof(u32)) { in jr_outentry_get()
226 u32 desc; in jr_outentry_get()
227 u32 jrstatus; in jr_outentry_get()
235 u32 jrstatus; /* Status for completed descriptor */ in jr_outentry_get()
243 #define SIZEOF_JR_OUTENTRY (caam_ptr_sz + sizeof(u32))
248 u32 unused; in jr_outentry_desc()
255 static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx) in jr_outentry_jrstatus()
258 u32 jrstatus; in jr_outentry_jrstatus()
267 if (caam_ptr_sz == sizeof(u32)) { in jr_inpentry_set()
268 u32 *inpentry = inpring; in jr_inpentry_set()
283 u32 crca; /* CRCA_VERSION */
284 u32 afha; /* AFHA_VERSION */
285 u32 kfha; /* KFHA_VERSION */
286 u32 pkha; /* PKHA_VERSION */
287 u32 aesa; /* AESA_VERSION */
288 u32 mdha; /* MDHA_VERSION */
289 u32 desa; /* DESA_VERSION */
290 u32 snw8a; /* SNW8A_VERSION */
291 u32 snw9a; /* SNW9A_VERSION */
292 u32 zuce; /* ZUCE_VERSION */
293 u32 zuca; /* ZUCA_VERSION */
294 u32 ccha; /* CCHA_VERSION */
295 u32 ptha; /* PTHA_VERSION */
296 u32 rng; /* RNG_VERSION */
297 u32 trng; /* TRNG_VERSION */
298 u32 aaha; /* AAHA_VERSION */
299 u32 rsvd[10];
300 u32 sr; /* SR_VERSION */
301 u32 dma; /* DMA_VERSION */
302 u32 ai; /* AI_VERSION */
303 u32 qi; /* QI_VERSION */
304 u32 jr; /* JR_VERSION */
305 u32 deco; /* DECO_VERSION */
406 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
407 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
416 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
417 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
422 u32 faultliodn; /* FALR - Fault Address LIODN */
423 u32 faultdetail; /* FADR - Fault Addr Detail */
424 u32 rsvd2;
427 u32 status; /* CSTA - CAAM Status */
431 u32 rtic_id; /* RVID - RTIC Version ID */
434 u32 ccb_id; /* CCBVID - CCB Version ID */
435 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
436 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
437 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
438 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
443 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
444 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
453 u32 liodn_ms; /* lock and make-trusted control bits */
454 u32 liodn_ls; /* LIODN for non-sequence and seq access */
459 u32 rsvd1;
460 u32 pidr; /* partition ID, DECO */
466 u32 mode; /* RTSTMODEx - Test mode */
467 u32 rsvd1[3];
468 u32 reset; /* RTSTRESETx - Test reset control */
469 u32 rsvd2[3];
470 u32 status; /* RTSTSSTATUSx - Test status */
471 u32 rsvd3;
472 u32 errstat; /* RTSTERRSTATx - Test error status */
473 u32 rsvd4;
474 u32 errctl; /* RTSTERRCTLx - Test error control */
475 u32 rsvd5;
476 u32 entropy; /* RTSTENTROPYx - Test entropy */
477 u32 rsvd6[15];
478 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
479 u32 rsvd7;
480 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
481 u32 rsvd8;
482 u32 verifdata; /* RTSTVERIFDx - Test verification data */
483 u32 rsvd9;
484 u32 xkey; /* RTSTXKEYx - Test XKEY */
485 u32 rsvd10;
486 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
487 u32 rsvd11;
488 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
489 u32 rsvd12;
490 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
491 u32 rsvd13[2];
492 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
493 u32 rsvd14[15];
510 u32 rtmctl; /* misc. control register */
511 u32 rtscmisc; /* statistical check misc. register */
512 u32 rtpkrrng; /* poker range register */
514 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
515 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
521 u32 rtsdctl; /* seed control register */
523 u32 rtsblim; /* PRGM=1: sparse bit limit register */
524 u32 rttotsam; /* PRGM=0: total samples register */
526 u32 rtfrqmin; /* frequency count min. limit register */
529 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
530 u32 rtfrqcnt; /* PRGM=0: freq. count register */
532 u32 rsvd1[40];
540 u32 rdsta;
541 u32 rsvd2[15];
563 u32 rsvd1;
564 u32 mcr; /* MCFG Master Config Register */
565 u32 rsvd2;
566 u32 scfgr; /* SCFGR, Security Config Register */
571 u32 rsvd3[11];
572 u32 jrstart; /* JRSTART - Job Ring Start Register */
574 u32 rsvd4[5];
575 u32 deco_rsr; /* DECORSR - Deco Request Source */
576 u32 rsvd11;
577 u32 deco_rq; /* DECORR - DECO Request */
579 u32 rsvd5[22];
582 u32 deco_avail; /* DAR - DECO availability */
583 u32 deco_reset; /* DRR - DECO reset */
584 u32 rsvd6[182];
588 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
589 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
590 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
591 u32 rsvd7[32];
593 u32 rsvd8[70];
602 u32 rsvd9[416];
661 u32 rsvd1;
662 u32 inpring_size; /* IRSx - Input ring size */
663 u32 rsvd2;
664 u32 inpring_avail; /* IRSAx - Input ring room remaining */
665 u32 rsvd3;
666 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
670 u32 rsvd4;
671 u32 outring_size; /* ORSx - Output ring size */
672 u32 rsvd5;
673 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
674 u32 rsvd6;
675 u32 outring_used; /* ORSFx - Output ring slots full */
678 u32 rsvd7;
679 u32 jroutstatus; /* JRSTAx - JobR output status */
680 u32 rsvd8;
681 u32 jrintstatus; /* JRINTx - JobR interrupt status */
682 u32 rconfig_hi; /* JRxCFG - Ring configuration */
683 u32 rconfig_lo;
686 u32 rsvd9;
687 u32 inp_rdidx; /* IRRIx - Input ring read index */
688 u32 rsvd10;
689 u32 out_wtidx; /* ORWIx - Output ring write index */
692 u32 rsvd11;
693 u32 jrcommand; /* JRCRx - JobR command */
695 u32 rsvd12[900];
830 u32 rsvd;
831 u32 length;
839 u32 memhash_be[32];
840 u32 memhash_le[32];
845 u32 rsvd1;
846 u32 status; /* RSTA - Status */
847 u32 rsvd2;
848 u32 cmd; /* RCMD - Command */
849 u32 rsvd3;
850 u32 ctrl; /* RCTL - Control */
851 u32 rsvd4;
852 u32 throttle; /* RTHR - Throttle */
853 u32 rsvd5[2];
855 u32 rsvd6;
856 u32 rend; /* REND - Endian corrections */
857 u32 rsvd7[50];
861 u32 rsvd8[32];
865 u32 rsvd_3[640];
874 u32 qi_control_hi; /* QICTL - QI Control */
875 u32 qi_control_lo;
876 u32 rsvd1;
877 u32 qi_status; /* QISTA - QI Status */
878 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
879 u32 qi_deq_cfg_lo;
880 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
881 u32 qi_enq_cfg_lo;
882 u32 rsvd2[1016];
922 u32 elen; /* E, F bits + 30-bit length */
923 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
936 u32 rsvd1;
937 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
938 u32 rsvd2;
939 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
940 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
941 u32 cls1_datasize_lo;
942 u32 rsvd3;
943 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
944 u32 rsvd4[5];
945 u32 cha_ctrl; /* CCTLR - CHA control */
946 u32 rsvd5;
947 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
948 u32 rsvd6;
949 u32 clr_written; /* CxCWR - Clear-Written */
950 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
951 u32 ccb_status_lo;
952 u32 rsvd7[3];
953 u32 aad_size; /* CxAADSZR - Current AAD Size */
954 u32 rsvd8;
955 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
956 u32 rsvd9[7];
957 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
958 u32 rsvd10;
959 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
960 u32 rsvd11;
961 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
962 u32 rsvd12;
963 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
964 u32 rsvd13[24];
965 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
966 u32 rsvd14[48];
967 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
968 u32 rsvd15[121];
969 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
970 u32 rsvd16;
971 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
972 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
973 u32 cls2_datasize_lo;
974 u32 rsvd17;
975 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
976 u32 rsvd18[56];
977 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
978 u32 rsvd19[46];
979 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
980 u32 rsvd20[84];
981 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
982 u32 inp_infofifo_lo;
983 u32 rsvd21[2];
985 u32 rsvd22[2];
987 u32 rsvd23[2];
988 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
989 u32 jr_ctl_lo;
992 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
993 u32 op_status_lo;
994 u32 rsvd24[2];
995 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
996 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
997 u32 rsvd26[6];
999 u32 rsvd27[8];
1001 u32 rsvd28[16];
1003 u32 rsvd29[48];
1004 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
1005 u32 rscvd30[193];
1009 u32 desc_dbg; /* DxDDR - DECO Debug Register */
1010 u32 rsvd31[13];
1013 u32 dbg_exec; /* DxDER - DECO Debug Exec Register */
1014 u32 rsvd32[112];