352 	vqx_ctl.u = readq(cptvf->reg_base + OTX_CPT_VQX_CTL(0));  in cptvf_write_vq_ctl()
361 	vqx_dbell.u = readq(cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0));  in otx_cptvf_write_vq_doorbell()
370 	vqx_inprg.u = readq(cptvf->reg_base + OTX_CPT_VQX_INPROG(0));  in cptvf_write_vq_inprog()
379 	vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_write_vq_done_numwait()
388 	vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_read_vq_done_numwait()
396 	vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_write_vq_done_timewait()
406 	vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_read_vq_done_timewait()
414 	vqx_misc_ena.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0));  in cptvf_enable_swerr_interrupts()
424 	vqx_misc_ena.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0));  in cptvf_enable_mbox_interrupts()
434 	vqx_done_ena.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_ENA_W1S(0));  in cptvf_enable_done_interrupts()
444 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_dovf_intr()
454 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_irde_intr()
464 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_nwrp_intr()
474 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_mbox_intr()
484 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_swerr_intr()
492 	return readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_read_vf_misc_intr_status()
555 	vqx_done.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE(0));  in cptvf_read_vq_done_count()
564 	vqx_dack_cnt.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_ACK(0));  in cptvf_write_vq_done_ack()