Lines Matching refs:chan
218 struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; member
221 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) in stm32_dma_get_dev() argument
223 return container_of(chan->vchan.chan.device, struct stm32_dma_device, in stm32_dma_get_dev()
229 return container_of(c, struct stm32_dma_chan, vchan.chan); in to_stm32_dma_chan()
237 static struct device *chan2dev(struct stm32_dma_chan *chan) in chan2dev() argument
239 return &chan->vchan.chan.dev->device; in chan2dev()
252 static int stm32_dma_get_width(struct stm32_dma_chan *chan, in stm32_dma_get_width() argument
263 dev_err(chan2dev(chan), "Dma bus width not supported\n"); in stm32_dma_get_width()
350 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) in stm32_dma_get_burst() argument
363 dev_err(chan2dev(chan), "Dma burst size not supported\n"); in stm32_dma_get_burst()
368 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan, in stm32_dma_set_fifo_config() argument
371 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
372 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
376 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
379 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
386 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_slave_config() local
388 memcpy(&chan->dma_sconfig, config, sizeof(*config)); in stm32_dma_slave_config()
390 chan->config_init = true; in stm32_dma_slave_config()
395 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) in stm32_dma_irq_status() argument
397 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_irq_status()
408 if (chan->id & 4) in stm32_dma_irq_status()
413 flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); in stm32_dma_irq_status()
418 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) in stm32_dma_irq_clear() argument
420 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_irq_clear()
431 dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); in stm32_dma_irq_clear()
433 if (chan->id & 4) in stm32_dma_irq_clear()
439 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan) in stm32_dma_disable_chan() argument
441 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_disable_chan()
444 id = chan->id; in stm32_dma_disable_chan()
460 static void stm32_dma_stop(struct stm32_dma_chan *chan) in stm32_dma_stop() argument
462 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_stop()
467 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_stop()
469 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_stop()
470 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_stop()
472 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); in stm32_dma_stop()
475 ret = stm32_dma_disable_chan(chan); in stm32_dma_stop()
480 status = stm32_dma_irq_status(chan); in stm32_dma_stop()
482 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", in stm32_dma_stop()
484 stm32_dma_irq_clear(chan, status); in stm32_dma_stop()
487 chan->busy = false; in stm32_dma_stop()
492 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_terminate_all() local
496 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
498 if (chan->desc) { in stm32_dma_terminate_all()
499 vchan_terminate_vdesc(&chan->desc->vdesc); in stm32_dma_terminate_all()
500 if (chan->busy) in stm32_dma_terminate_all()
501 stm32_dma_stop(chan); in stm32_dma_terminate_all()
502 chan->desc = NULL; in stm32_dma_terminate_all()
505 vchan_get_all_descriptors(&chan->vchan, &head); in stm32_dma_terminate_all()
506 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
507 vchan_dma_desc_free_list(&chan->vchan, &head); in stm32_dma_terminate_all()
514 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_synchronize() local
516 vchan_synchronize(&chan->vchan); in stm32_dma_synchronize()
519 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) in stm32_dma_dump_reg() argument
521 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_dump_reg()
522 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_dump_reg()
523 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_dump_reg()
524 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); in stm32_dma_dump_reg()
525 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); in stm32_dma_dump_reg()
526 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); in stm32_dma_dump_reg()
527 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_dump_reg()
529 dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); in stm32_dma_dump_reg()
530 dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr); in stm32_dma_dump_reg()
531 dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar); in stm32_dma_dump_reg()
532 dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar); in stm32_dma_dump_reg()
533 dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar); in stm32_dma_dump_reg()
534 dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr); in stm32_dma_dump_reg()
537 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
539 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) in stm32_dma_start_transfer() argument
541 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_start_transfer()
548 ret = stm32_dma_disable_chan(chan); in stm32_dma_start_transfer()
552 if (!chan->desc) { in stm32_dma_start_transfer()
553 vdesc = vchan_next_desc(&chan->vchan); in stm32_dma_start_transfer()
559 chan->desc = to_stm32_dma_desc(vdesc); in stm32_dma_start_transfer()
560 chan->next_sg = 0; in stm32_dma_start_transfer()
563 if (chan->next_sg == chan->desc->num_sgs) in stm32_dma_start_transfer()
564 chan->next_sg = 0; in stm32_dma_start_transfer()
566 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_start_transfer()
570 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
571 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); in stm32_dma_start_transfer()
572 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); in stm32_dma_start_transfer()
573 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); in stm32_dma_start_transfer()
574 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); in stm32_dma_start_transfer()
575 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); in stm32_dma_start_transfer()
577 chan->next_sg++; in stm32_dma_start_transfer()
580 status = stm32_dma_irq_status(chan); in stm32_dma_start_transfer()
582 stm32_dma_irq_clear(chan, status); in stm32_dma_start_transfer()
584 if (chan->desc->cyclic) in stm32_dma_start_transfer()
585 stm32_dma_configure_next_sg(chan); in stm32_dma_start_transfer()
587 stm32_dma_dump_reg(chan); in stm32_dma_start_transfer()
591 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
593 chan->busy = true; in stm32_dma_start_transfer()
595 dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); in stm32_dma_start_transfer()
598 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) in stm32_dma_configure_next_sg() argument
600 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_configure_next_sg()
604 id = chan->id; in stm32_dma_configure_next_sg()
608 if (chan->next_sg == chan->desc->num_sgs) in stm32_dma_configure_next_sg()
609 chan->next_sg = 0; in stm32_dma_configure_next_sg()
611 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_configure_next_sg()
616 dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n", in stm32_dma_configure_next_sg()
621 dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n", in stm32_dma_configure_next_sg()
627 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan) in stm32_dma_handle_chan_done() argument
629 if (chan->desc) { in stm32_dma_handle_chan_done()
630 if (chan->desc->cyclic) { in stm32_dma_handle_chan_done()
631 vchan_cyclic_callback(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
632 chan->next_sg++; in stm32_dma_handle_chan_done()
633 stm32_dma_configure_next_sg(chan); in stm32_dma_handle_chan_done()
635 chan->busy = false; in stm32_dma_handle_chan_done()
636 if (chan->next_sg == chan->desc->num_sgs) { in stm32_dma_handle_chan_done()
637 vchan_cookie_complete(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
638 chan->desc = NULL; in stm32_dma_handle_chan_done()
640 stm32_dma_start_transfer(chan); in stm32_dma_handle_chan_done()
647 struct stm32_dma_chan *chan = devid; in stm32_dma_chan_irq() local
648 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_chan_irq()
651 spin_lock(&chan->vchan.lock); in stm32_dma_chan_irq()
653 status = stm32_dma_irq_status(chan); in stm32_dma_chan_irq()
654 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_chan_irq()
655 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_chan_irq()
658 stm32_dma_irq_clear(chan, STM32_DMA_FEI); in stm32_dma_chan_irq()
663 dev_err(chan2dev(chan), "FIFO Error\n"); in stm32_dma_chan_irq()
665 dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); in stm32_dma_chan_irq()
669 stm32_dma_irq_clear(chan, STM32_DMA_DMEI); in stm32_dma_chan_irq()
672 dev_dbg(chan2dev(chan), "Direct mode overrun\n"); in stm32_dma_chan_irq()
676 stm32_dma_irq_clear(chan, STM32_DMA_TCI); in stm32_dma_chan_irq()
678 stm32_dma_handle_chan_done(chan); in stm32_dma_chan_irq()
683 stm32_dma_irq_clear(chan, STM32_DMA_HTI); in stm32_dma_chan_irq()
688 stm32_dma_irq_clear(chan, status); in stm32_dma_chan_irq()
689 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); in stm32_dma_chan_irq()
691 dev_err(chan2dev(chan), "chan disabled by HW\n"); in stm32_dma_chan_irq()
694 spin_unlock(&chan->vchan.lock); in stm32_dma_chan_irq()
701 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_issue_pending() local
704 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
705 if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { in stm32_dma_issue_pending()
706 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); in stm32_dma_issue_pending()
707 stm32_dma_start_transfer(chan); in stm32_dma_issue_pending()
710 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
713 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, in stm32_dma_set_xfer_param() argument
724 src_addr_width = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
725 dst_addr_width = chan->dma_sconfig.dst_addr_width; in stm32_dma_set_xfer_param()
726 src_maxburst = chan->dma_sconfig.src_maxburst; in stm32_dma_set_xfer_param()
727 dst_maxburst = chan->dma_sconfig.dst_maxburst; in stm32_dma_set_xfer_param()
728 fifoth = chan->threshold; in stm32_dma_set_xfer_param()
733 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); in stm32_dma_set_xfer_param()
743 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); in stm32_dma_set_xfer_param()
750 chan->mem_width = src_addr_width; in stm32_dma_set_xfer_param()
751 src_bus_width = stm32_dma_get_width(chan, src_addr_width); in stm32_dma_set_xfer_param()
767 src_burst_size = stm32_dma_get_burst(chan, src_best_burst); in stm32_dma_set_xfer_param()
778 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
780 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); in stm32_dma_set_xfer_param()
783 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; in stm32_dma_set_xfer_param()
789 src_bus_width = stm32_dma_get_width(chan, src_addr_width); in stm32_dma_set_xfer_param()
798 chan->mem_burst = src_best_burst; in stm32_dma_set_xfer_param()
799 src_burst_size = stm32_dma_get_burst(chan, src_best_burst); in stm32_dma_set_xfer_param()
806 chan->mem_width = dst_addr_width; in stm32_dma_set_xfer_param()
807 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); in stm32_dma_set_xfer_param()
823 chan->mem_burst = dst_best_burst; in stm32_dma_set_xfer_param()
824 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); in stm32_dma_set_xfer_param()
835 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
837 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); in stm32_dma_set_xfer_param()
840 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; in stm32_dma_set_xfer_param()
841 *buswidth = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
845 dev_err(chan2dev(chan), "Dma direction is not supported\n"); in stm32_dma_set_xfer_param()
849 stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst); in stm32_dma_set_xfer_param()
852 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | in stm32_dma_set_xfer_param()
855 chan->chan_reg.dma_scr |= dma_scr; in stm32_dma_set_xfer_param()
870 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_prep_slave_sg() local
877 if (!chan->config_init) { in stm32_dma_prep_slave_sg()
878 dev_err(chan2dev(chan), "dma channel is not configured\n"); in stm32_dma_prep_slave_sg()
883 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len); in stm32_dma_prep_slave_sg()
892 if (chan->dma_sconfig.device_fc) in stm32_dma_prep_slave_sg()
893 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
895 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
898 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, in stm32_dma_prep_slave_sg()
908 dev_err(chan2dev(chan), "nb items not supported\n"); in stm32_dma_prep_slave_sg()
913 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_slave_sg()
914 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_slave_sg()
915 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_slave_sg()
924 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_slave_sg()
936 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_prep_dma_cyclic() local
943 dev_err(chan2dev(chan), "Invalid buffer/period len\n"); in stm32_dma_prep_dma_cyclic()
947 if (!chan->config_init) { in stm32_dma_prep_dma_cyclic()
948 dev_err(chan2dev(chan), "dma channel is not configured\n"); in stm32_dma_prep_dma_cyclic()
953 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); in stm32_dma_prep_dma_cyclic()
963 if (chan->busy) { in stm32_dma_prep_dma_cyclic()
964 dev_err(chan2dev(chan), "Request not allowed when dma busy\n"); in stm32_dma_prep_dma_cyclic()
968 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len, in stm32_dma_prep_dma_cyclic()
975 dev_err(chan2dev(chan), "number of items not supported\n"); in stm32_dma_prep_dma_cyclic()
981 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; in stm32_dma_prep_dma_cyclic()
983 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_prep_dma_cyclic()
986 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_dma_cyclic()
998 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_dma_cyclic()
999 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_dma_cyclic()
1000 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_dma_cyclic()
1010 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_cyclic()
1017 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_prep_dma_memcpy() local
1029 threshold = chan->threshold; in stm32_dma_prep_dma_memcpy()
1039 dma_burst = stm32_dma_get_burst(chan, best_burst); in stm32_dma_prep_dma_memcpy()
1062 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_memcpy()
1065 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) in stm32_dma_get_remaining_bytes() argument
1068 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_get_remaining_bytes()
1070 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_get_remaining_bytes()
1072 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_get_remaining_bytes()
1089 static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan) in stm32_dma_is_current_sg() argument
1091 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_is_current_sg()
1095 id = chan->id; in stm32_dma_is_current_sg()
1101 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_is_current_sg()
1113 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, in stm32_dma_desc_residue() argument
1120 struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_desc_residue()
1148 residue = stm32_dma_get_remaining_bytes(chan); in stm32_dma_desc_residue()
1150 if (!stm32_dma_is_current_sg(chan)) { in stm32_dma_desc_residue()
1152 if (n_sg == chan->desc->num_sgs) in stm32_dma_desc_residue()
1164 if (!chan->desc->cyclic || n_sg != 0) in stm32_dma_desc_residue()
1168 if (!chan->mem_burst) in stm32_dma_desc_residue()
1171 burst_size = chan->mem_burst * chan->mem_width; in stm32_dma_desc_residue()
1183 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_tx_status() local
1193 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1194 vdesc = vchan_find_desc(&chan->vchan, cookie); in stm32_dma_tx_status()
1195 if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) in stm32_dma_tx_status()
1196 residue = stm32_dma_desc_residue(chan, chan->desc, in stm32_dma_tx_status()
1197 chan->next_sg); in stm32_dma_tx_status()
1199 residue = stm32_dma_desc_residue(chan, in stm32_dma_tx_status()
1203 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1210 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_alloc_chan_resources() local
1211 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_alloc_chan_resources()
1214 chan->config_init = false; in stm32_dma_alloc_chan_resources()
1220 ret = stm32_dma_disable_chan(chan); in stm32_dma_alloc_chan_resources()
1229 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_free_chan_resources() local
1230 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_free_chan_resources()
1233 dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); in stm32_dma_free_chan_resources()
1235 if (chan->busy) { in stm32_dma_free_chan_resources()
1236 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1237 stm32_dma_stop(chan); in stm32_dma_free_chan_resources()
1238 chan->desc = NULL; in stm32_dma_free_chan_resources()
1239 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1245 stm32_dma_clear_reg(&chan->chan_reg); in stm32_dma_free_chan_resources()
1246 chan->threshold = 0; in stm32_dma_free_chan_resources()
1254 static void stm32_dma_set_config(struct stm32_dma_chan *chan, in stm32_dma_set_config() argument
1257 stm32_dma_clear_reg(&chan->chan_reg); in stm32_dma_set_config()
1259 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; in stm32_dma_set_config()
1260 chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line); in stm32_dma_set_config()
1263 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; in stm32_dma_set_config()
1265 chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features); in stm32_dma_set_config()
1267 chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE; in stm32_dma_set_config()
1269 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF; in stm32_dma_set_config()
1278 struct stm32_dma_chan *chan; in stm32_dma_of_xlate() local
1297 chan = &dmadev->chan[cfg.channel_id]; in stm32_dma_of_xlate()
1299 c = dma_get_slave_channel(&chan->vchan.chan); in stm32_dma_of_xlate()
1305 stm32_dma_set_config(chan, &cfg); in stm32_dma_of_xlate()
1318 struct stm32_dma_chan *chan; in stm32_dma_probe() local
1402 chan = &dmadev->chan[i]; in stm32_dma_probe()
1403 chan->id = i; in stm32_dma_probe()
1404 chan->vchan.desc_free = stm32_dma_desc_free; in stm32_dma_probe()
1405 vchan_init(&chan->vchan, dd); in stm32_dma_probe()
1413 chan = &dmadev->chan[i]; in stm32_dma_probe()
1417 chan->irq = ret; in stm32_dma_probe()
1419 ret = devm_request_irq(&pdev->dev, chan->irq, in stm32_dma_probe()
1421 dev_name(chan2dev(chan)), chan); in stm32_dma_probe()