Lines Matching refs:crtc_offset
262 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
265 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_page_flip()
267 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
270 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
273 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
276 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
604 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_fmt()
655 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v11_0_line_buffer_adjust()
657 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_line_buffer_adjust()
1152 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1154 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1155 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1158 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1161 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1162 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1165 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1167 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v11_0_program_watermarks()
1885 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v11_0_grph_enable()
1887 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_grph_enable()
2063 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2066 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2068 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2070 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2072 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2074 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2076 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v11_0_crtc_do_set_base()
2077 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v11_0_crtc_do_set_base()
2084 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2089 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2094 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2095 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2096 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2097 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2098 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v11_0_crtc_do_set_base()
2099 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v11_0_crtc_do_set_base()
2102 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v11_0_crtc_do_set_base()
2106 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2111 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2115 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2119 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2144 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v11_0_set_interleave()
2149 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_set_interleave()
2163 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2165 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2167 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2169 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2171 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2173 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2175 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2177 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2178 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2179 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2181 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2182 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2183 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2185 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2186 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v11_0_crtc_load_lut()
2188 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2193 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_load_lut()
2199 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2203 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2205 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2207 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2209 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2211 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2213 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2215 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2218 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2222 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2224 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2364 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v11_0_lock_cursor()
2369 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v11_0_lock_cursor()
2378 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_hide_cursor()
2380 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_hide_cursor()
2389 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2391 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2394 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_show_cursor()
2397 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_show_cursor()
2424 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v11_0_cursor_move_locked()
2425 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v11_0_cursor_move_locked()
2426 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_cursor_move_locked()
2819 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2822 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2825 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2828 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2831 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2834 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v11_0_crtc_init()