191 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?  in dce_v8_0_page_flip()
194 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,  in dce_v8_0_page_flip()
197 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_page_flip()
200 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_page_flip()
203 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v8_0_page_flip()
515 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v8_0_program_fmt()
566 	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,  in dce_v8_0_line_buffer_adjust()
1061 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_program_watermarks()
1065 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v8_0_program_watermarks()
1066 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_program_watermarks()
1070 	tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_program_watermarks()
1073 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v8_0_program_watermarks()
1074 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_program_watermarks()
1078 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);  in dce_v8_0_program_watermarks()
1772 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);  in dce_v8_0_grph_enable()
1774 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_grph_enable()
1936 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1938 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1940 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1942 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1944 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1946 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v8_0_crtc_do_set_base()
1947 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);  in dce_v8_0_crtc_do_set_base()
1954 	WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1961 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1962 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1963 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1964 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1965 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);  in dce_v8_0_crtc_do_set_base()
1966 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);  in dce_v8_0_crtc_do_set_base()
1969 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);  in dce_v8_0_crtc_do_set_base()
1973 	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1978 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1982 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1986 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
2011 		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,  in dce_v8_0_set_interleave()
2014 		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_set_interleave()
2027 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2030 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2032 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2034 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2038 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2040 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2041 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2042 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2044 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v8_0_crtc_load_lut()
2045 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v8_0_crtc_load_lut()
2046 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v8_0_crtc_load_lut()
2048 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2049 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);  in dce_v8_0_crtc_load_lut()
2051 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2056 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2062 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2066 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2069 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2072 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2076 	WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2080 	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2195 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v8_0_lock_cursor()
2200 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);  in dce_v8_0_lock_cursor()
2208 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_hide_cursor()
2218 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_show_cursor()
2220 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_show_cursor()
2223 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_show_cursor()
2253 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);  in dce_v8_0_cursor_move_locked()
2254 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);  in dce_v8_0_cursor_move_locked()
2255 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,  in dce_v8_0_cursor_move_locked()
2623 	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];  in dce_v8_0_crtc_init()