Lines Matching refs:GC_HWIP
1489 case GC_HWIP: in gfx_v10_get_rlcg_flag()
1532 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4; in gfx_v10_rlcg_rw()
1534 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4; in gfx_v10_rlcg_rw()
1536 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4; in gfx_v10_rlcg_rw()
1538 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; in gfx_v10_rlcg_rw()
1542 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX] in gfx_v10_rlcg_rw()
1546 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4; in gfx_v10_rlcg_rw()
1549 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; in gfx_v10_rlcg_rw()
1550 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; in gfx_v10_rlcg_rw()
8211 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + in gfx_v10_0_apply_medium_grain_clock_gating_workaround()
8219 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + in gfx_v10_0_apply_medium_grain_clock_gating_workaround()
8228 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + in gfx_v10_0_apply_medium_grain_clock_gating_workaround()