Lines Matching refs:adev
181 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, in nv_query_video_codecs() argument
184 switch (adev->asic_type) { in nv_query_video_codecs()
186 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
234 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg() argument
237 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
238 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
240 return amdgpu_device_indirect_rreg(adev, address, data, reg); in nv_pcie_rreg()
243 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_wreg() argument
247 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
248 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
250 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in nv_pcie_wreg()
253 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg64() argument
256 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg64()
257 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg64()
259 return amdgpu_device_indirect_rreg64(adev, address, data, reg); in nv_pcie_rreg64()
262 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_port_rreg() argument
266 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); in nv_pcie_port_rreg()
267 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); in nv_pcie_port_rreg()
269 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in nv_pcie_port_rreg()
273 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in nv_pcie_port_rreg()
277 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in nv_pcie_wreg64() argument
281 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg64()
282 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg64()
284 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); in nv_pcie_wreg64()
287 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_port_wreg() argument
291 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); in nv_pcie_port_wreg()
292 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); in nv_pcie_port_wreg()
294 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in nv_pcie_port_wreg()
299 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in nv_pcie_port_wreg()
302 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) in nv_didt_rreg() argument
310 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_rreg()
313 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_rreg()
317 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_didt_wreg() argument
324 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_wreg()
327 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_wreg()
330 static u32 nv_get_config_memsize(struct amdgpu_device *adev) in nv_get_config_memsize() argument
332 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
335 static u32 nv_get_xclk(struct amdgpu_device *adev) in nv_get_xclk() argument
337 return adev->clock.spll.reference_freq; in nv_get_xclk()
341 void nv_grbm_select(struct amdgpu_device *adev, in nv_grbm_select() argument
353 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) in nv_vga_set_state() argument
358 static bool nv_read_disabled_bios(struct amdgpu_device *adev) in nv_read_disabled_bios() argument
364 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, in nv_read_bios_from_rom() argument
376 if (adev->flags & AMD_IS_APU) in nv_read_bios_from_rom()
383 adev->smuio.funcs->get_rom_index_offset(adev); in nv_read_bios_from_rom()
385 adev->smuio.funcs->get_rom_data_offset(adev); in nv_read_bios_from_rom()
418 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
423 mutex_lock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
425 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
430 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in nv_read_indexed_register()
431 mutex_unlock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
435 static uint32_t nv_get_register_value(struct amdgpu_device *adev, in nv_get_register_value() argument
440 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
443 return adev->gfx.config.gb_addr_config; in nv_get_register_value()
448 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
457 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ in nv_read_register()
459 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) in nv_read_register()
462 *value = nv_get_register_value(adev, in nv_read_register()
470 static int nv_asic_mode2_reset(struct amdgpu_device *adev) in nv_asic_mode2_reset() argument
475 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in nv_asic_mode2_reset()
478 pci_clear_master(adev->pdev); in nv_asic_mode2_reset()
480 amdgpu_device_cache_pci_state(adev->pdev); in nv_asic_mode2_reset()
482 ret = amdgpu_dpm_mode2_reset(adev); in nv_asic_mode2_reset()
484 dev_err(adev->dev, "GPU mode2 reset failed\n"); in nv_asic_mode2_reset()
486 amdgpu_device_load_pci_state(adev->pdev); in nv_asic_mode2_reset()
489 for (i = 0; i < adev->usec_timeout; i++) { in nv_asic_mode2_reset()
490 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode2_reset()
497 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in nv_asic_mode2_reset()
503 nv_asic_reset_method(struct amdgpu_device *adev) in nv_asic_reset_method() argument
512 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in nv_asic_reset_method()
515 switch (adev->asic_type) { in nv_asic_reset_method()
525 if (amdgpu_dpm_is_baco_supported(adev)) in nv_asic_reset_method()
532 static int nv_asic_reset(struct amdgpu_device *adev) in nv_asic_reset() argument
536 switch (nv_asic_reset_method(adev)) { in nv_asic_reset()
538 dev_info(adev->dev, "PCI reset\n"); in nv_asic_reset()
539 ret = amdgpu_device_pci_reset(adev); in nv_asic_reset()
542 dev_info(adev->dev, "BACO reset\n"); in nv_asic_reset()
543 ret = amdgpu_dpm_baco_reset(adev); in nv_asic_reset()
546 dev_info(adev->dev, "MODE2 reset\n"); in nv_asic_reset()
547 ret = nv_asic_mode2_reset(adev); in nv_asic_reset()
550 dev_info(adev->dev, "MODE1 reset\n"); in nv_asic_reset()
551 ret = amdgpu_device_mode1_reset(adev); in nv_asic_reset()
558 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in nv_set_uvd_clocks() argument
564 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in nv_set_vce_clocks() argument
570 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) in nv_pcie_gen3_enable() argument
572 if (pci_is_root_bus(adev->pdev->bus)) in nv_pcie_gen3_enable()
578 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in nv_pcie_gen3_enable()
585 static void nv_program_aspm(struct amdgpu_device *adev) in nv_program_aspm() argument
587 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk()) in nv_program_aspm()
590 if (!(adev->flags & AMD_IS_APU) && in nv_program_aspm()
591 (adev->nbio.funcs->program_aspm)) in nv_program_aspm()
592 adev->nbio.funcs->program_aspm(adev); in nv_program_aspm()
596 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, in nv_enable_doorbell_aperture() argument
599 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); in nv_enable_doorbell_aperture()
600 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); in nv_enable_doorbell_aperture()
622 static int nv_reg_base_init(struct amdgpu_device *adev) in nv_reg_base_init() argument
627 r = amdgpu_discovery_reg_base_init(adev); in nv_reg_base_init()
634 amdgpu_discovery_harvest_ip(adev); in nv_reg_base_init()
635 if (nv_is_headless_sku(adev->pdev)) { in nv_reg_base_init()
636 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; in nv_reg_base_init()
637 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; in nv_reg_base_init()
644 switch (adev->asic_type) { in nv_reg_base_init()
646 navi10_reg_base_init(adev); in nv_reg_base_init()
649 navi14_reg_base_init(adev); in nv_reg_base_init()
652 navi12_reg_base_init(adev); in nv_reg_base_init()
656 sienna_cichlid_reg_base_init(adev); in nv_reg_base_init()
659 vangogh_reg_base_init(adev); in nv_reg_base_init()
662 dimgrey_cavefish_reg_base_init(adev); in nv_reg_base_init()
665 beige_goby_reg_base_init(adev); in nv_reg_base_init()
668 yellow_carp_reg_base_init(adev); in nv_reg_base_init()
671 cyan_skillfish_reg_base_init(adev); in nv_reg_base_init()
680 void nv_set_virt_ops(struct amdgpu_device *adev) in nv_set_virt_ops() argument
682 adev->virt.ops = &xgpu_nv_virt_ops; in nv_set_virt_ops()
685 int nv_set_ip_blocks(struct amdgpu_device *adev) in nv_set_ip_blocks() argument
689 if (adev->asic_type == CHIP_CYAN_SKILLFISH) { in nv_set_ip_blocks()
690 adev->nbio.funcs = &nbio_v2_3_funcs; in nv_set_ip_blocks()
691 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; in nv_set_ip_blocks()
692 } else if (adev->flags & AMD_IS_APU) { in nv_set_ip_blocks()
693 adev->nbio.funcs = &nbio_v7_2_funcs; in nv_set_ip_blocks()
694 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; in nv_set_ip_blocks()
696 adev->nbio.funcs = &nbio_v2_3_funcs; in nv_set_ip_blocks()
697 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; in nv_set_ip_blocks()
699 adev->hdp.funcs = &hdp_v5_0_funcs; in nv_set_ip_blocks()
701 if (adev->asic_type >= CHIP_SIENNA_CICHLID) in nv_set_ip_blocks()
702 adev->smuio.funcs = &smuio_v11_0_6_funcs; in nv_set_ip_blocks()
704 adev->smuio.funcs = &smuio_v11_0_funcs; in nv_set_ip_blocks()
706 if (adev->asic_type == CHIP_SIENNA_CICHLID) in nv_set_ip_blocks()
707 adev->gmc.xgmi.supported = true; in nv_set_ip_blocks()
710 r = nv_reg_base_init(adev); in nv_set_ip_blocks()
714 switch (adev->asic_type) { in nv_set_ip_blocks()
717 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
718 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
719 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
720 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
721 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
722 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
723 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
724 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
725 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
727 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
728 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
730 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
731 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
732 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
733 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
734 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
735 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in nv_set_ip_blocks()
736 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); in nv_set_ip_blocks()
737 if (adev->enable_mes) in nv_set_ip_blocks()
738 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); in nv_set_ip_blocks()
741 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
742 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
743 if (!amdgpu_sriov_vf(adev)) { in nv_set_ip_blocks()
744 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
745 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
747 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
748 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
750 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) in nv_set_ip_blocks()
751 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
752 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
753 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
755 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
756 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
758 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
759 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
760 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
761 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
762 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
763 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in nv_set_ip_blocks()
764 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
765 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); in nv_set_ip_blocks()
768 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
769 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
770 if (!amdgpu_sriov_vf(adev)) { in nv_set_ip_blocks()
771 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
772 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
773 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
775 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
776 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
777 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
779 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
780 is_support_sw_smu(adev)) in nv_set_ip_blocks()
781 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
782 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
783 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
785 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
786 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
788 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
789 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
790 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
791 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
792 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
793 if (adev->enable_mes) in nv_set_ip_blocks()
794 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); in nv_set_ip_blocks()
797 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
798 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
799 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
800 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
801 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
802 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
803 is_support_sw_smu(adev)) in nv_set_ip_blocks()
804 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
805 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
806 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
808 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
809 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
811 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
812 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
813 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
814 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
815 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
816 is_support_sw_smu(adev)) in nv_set_ip_blocks()
817 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
820 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
821 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
822 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
823 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
824 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
825 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
826 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
827 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
829 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
830 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
832 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
833 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
834 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
835 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
838 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
839 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
840 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
841 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
842 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
843 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
844 is_support_sw_smu(adev)) in nv_set_ip_blocks()
845 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
846 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
847 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
849 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
850 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
852 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
853 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
854 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
855 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
858 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
859 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
860 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
861 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
862 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
863 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
864 is_support_sw_smu(adev)) in nv_set_ip_blocks()
865 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
866 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
867 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
868 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
869 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
871 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
872 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
874 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
875 is_support_sw_smu(adev)) in nv_set_ip_blocks()
876 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
877 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
880 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
881 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
882 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
883 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
884 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); in nv_set_ip_blocks()
885 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); in nv_set_ip_blocks()
886 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
887 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
888 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
889 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
890 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
891 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
893 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
894 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
896 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
897 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
900 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
901 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
902 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
903 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { in nv_set_ip_blocks()
904 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
905 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); in nv_set_ip_blocks()
906 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
908 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
909 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in nv_set_ip_blocks()
910 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
911 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
920 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) in nv_get_rev_id() argument
922 return adev->nbio.funcs->get_rev_id(adev); in nv_get_rev_id()
925 static bool nv_need_full_reset(struct amdgpu_device *adev) in nv_need_full_reset() argument
930 static bool nv_need_reset_on_init(struct amdgpu_device *adev) in nv_need_reset_on_init() argument
934 if (adev->flags & AMD_IS_APU) in nv_need_reset_on_init()
947 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) in nv_get_pcie_replay_count() argument
957 static void nv_init_doorbell_index(struct amdgpu_device *adev) in nv_init_doorbell_index() argument
959 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
960 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in nv_init_doorbell_index()
961 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in nv_init_doorbell_index()
962 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in nv_init_doorbell_index()
963 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in nv_init_doorbell_index()
964 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in nv_init_doorbell_index()
965 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in nv_init_doorbell_index()
966 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in nv_init_doorbell_index()
967 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in nv_init_doorbell_index()
968 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in nv_init_doorbell_index()
969 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in nv_init_doorbell_index()
970 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in nv_init_doorbell_index()
971 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in nv_init_doorbell_index()
972 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; in nv_init_doorbell_index()
973 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in nv_init_doorbell_index()
974 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in nv_init_doorbell_index()
975 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; in nv_init_doorbell_index()
976 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; in nv_init_doorbell_index()
977 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in nv_init_doorbell_index()
978 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in nv_init_doorbell_index()
979 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in nv_init_doorbell_index()
980 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in nv_init_doorbell_index()
981 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in nv_init_doorbell_index()
982 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in nv_init_doorbell_index()
983 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in nv_init_doorbell_index()
985 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in nv_init_doorbell_index()
986 adev->doorbell_index.sdma_doorbell_range = 20; in nv_init_doorbell_index()
989 static void nv_pre_asic_init(struct amdgpu_device *adev) in nv_pre_asic_init() argument
993 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, in nv_update_umd_stable_pstate() argument
997 amdgpu_gfx_rlc_enter_safe_mode(adev); in nv_update_umd_stable_pstate()
999 amdgpu_gfx_rlc_exit_safe_mode(adev); in nv_update_umd_stable_pstate()
1001 if (adev->gfx.funcs->update_perfmon_mgcg) in nv_update_umd_stable_pstate()
1002 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in nv_update_umd_stable_pstate()
1004 if (!(adev->flags & AMD_IS_APU) && in nv_update_umd_stable_pstate()
1005 (adev->nbio.funcs->enable_aspm)) in nv_update_umd_stable_pstate()
1006 adev->nbio.funcs->enable_aspm(adev, !enter); in nv_update_umd_stable_pstate()
1036 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_early_init() local
1038 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
1039 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
1040 adev->smc_rreg = NULL; in nv_common_early_init()
1041 adev->smc_wreg = NULL; in nv_common_early_init()
1042 adev->pcie_rreg = &nv_pcie_rreg; in nv_common_early_init()
1043 adev->pcie_wreg = &nv_pcie_wreg; in nv_common_early_init()
1044 adev->pcie_rreg64 = &nv_pcie_rreg64; in nv_common_early_init()
1045 adev->pcie_wreg64 = &nv_pcie_wreg64; in nv_common_early_init()
1046 adev->pciep_rreg = &nv_pcie_port_rreg; in nv_common_early_init()
1047 adev->pciep_wreg = &nv_pcie_port_wreg; in nv_common_early_init()
1050 adev->uvd_ctx_rreg = NULL; in nv_common_early_init()
1051 adev->uvd_ctx_wreg = NULL; in nv_common_early_init()
1053 adev->didt_rreg = &nv_didt_rreg; in nv_common_early_init()
1054 adev->didt_wreg = &nv_didt_wreg; in nv_common_early_init()
1056 adev->asic_funcs = &nv_asic_funcs; in nv_common_early_init()
1058 adev->rev_id = nv_get_rev_id(adev); in nv_common_early_init()
1059 adev->external_rev_id = 0xff; in nv_common_early_init()
1060 switch (adev->asic_type) { in nv_common_early_init()
1062 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1077 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1081 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
1084 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1099 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1102 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
1105 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1121 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1129 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
1130 adev->rev_id = 0; in nv_common_early_init()
1131 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
1134 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1145 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1150 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
1152 adev->cg_flags = 0; in nv_common_early_init()
1153 adev->pg_flags = 0; in nv_common_early_init()
1155 adev->external_rev_id = adev->rev_id + 0x28; in nv_common_early_init()
1158 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1169 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1174 adev->external_rev_id = adev->rev_id + 0x32; in nv_common_early_init()
1178 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1193 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
1197 if (adev->apu_flags & AMD_APU_IS_VANGOGH) in nv_common_early_init()
1198 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
1201 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1212 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1217 adev->external_rev_id = adev->rev_id + 0x3c; in nv_common_early_init()
1220 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1230 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1234 adev->external_rev_id = adev->rev_id + 0x46; in nv_common_early_init()
1237 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1256 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
1260 if (adev->pdev->device == 0x1681) in nv_common_early_init()
1261 adev->external_rev_id = 0x20; in nv_common_early_init()
1263 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
1266 adev->cg_flags = 0; in nv_common_early_init()
1267 adev->pg_flags = 0; in nv_common_early_init()
1268 adev->external_rev_id = adev->rev_id + 0x82; in nv_common_early_init()
1275 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) in nv_common_early_init()
1276 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1280 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
1281 amdgpu_virt_init_setting(adev); in nv_common_early_init()
1282 xgpu_nv_mailbox_set_irq_funcs(adev); in nv_common_early_init()
1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_late_init() local
1292 if (amdgpu_sriov_vf(adev)) { in nv_common_late_init()
1293 xgpu_nv_mailbox_get_irq(adev); in nv_common_late_init()
1294 amdgpu_virt_update_sriov_video_codec(adev, in nv_common_late_init()
1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_sw_init() local
1306 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
1307 xgpu_nv_mailbox_add_irq_id(adev); in nv_common_sw_init()
1319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_init() local
1321 if (adev->nbio.funcs->apply_lc_spc_mode_wa) in nv_common_hw_init()
1322 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); in nv_common_hw_init()
1324 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) in nv_common_hw_init()
1325 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); in nv_common_hw_init()
1328 nv_pcie_gen3_enable(adev); in nv_common_hw_init()
1330 nv_program_aspm(adev); in nv_common_hw_init()
1332 adev->nbio.funcs->init_registers(adev); in nv_common_hw_init()
1337 if (adev->nbio.funcs->remap_hdp_registers) in nv_common_hw_init()
1338 adev->nbio.funcs->remap_hdp_registers(adev); in nv_common_hw_init()
1340 nv_enable_doorbell_aperture(adev, true); in nv_common_hw_init()
1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_fini() local
1350 nv_enable_doorbell_aperture(adev, false); in nv_common_hw_fini()
1357 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_suspend() local
1359 return nv_common_hw_fini(adev); in nv_common_suspend()
1364 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_resume() local
1366 return nv_common_hw_init(adev); in nv_common_resume()
1387 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_set_clockgating_state() local
1389 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1392 switch (adev->asic_type) { in nv_common_set_clockgating_state()
1400 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in nv_common_set_clockgating_state()
1402 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in nv_common_set_clockgating_state()
1404 adev->hdp.funcs->update_clock_gating(adev, in nv_common_set_clockgating_state()
1406 adev->smuio.funcs->update_rom_clock_gating(adev, in nv_common_set_clockgating_state()
1424 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_get_clockgating_state() local
1426 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
1429 adev->nbio.funcs->get_clockgating_state(adev, flags); in nv_common_get_clockgating_state()
1431 adev->hdp.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()
1433 adev->smuio.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()