Lines Matching refs:adev
154 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc15_query_video_codecs() argument
157 switch (adev->asic_type) { in soc15_query_video_codecs()
188 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
191 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
192 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
194 return amdgpu_device_indirect_rreg(adev, address, data, reg); in soc15_pcie_rreg()
197 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
201 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
202 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
204 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in soc15_pcie_wreg()
207 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg64() argument
210 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg64()
211 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg64()
213 return amdgpu_device_indirect_rreg64(adev, address, data, reg); in soc15_pcie_rreg64()
216 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in soc15_pcie_wreg64() argument
220 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg64()
221 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg64()
223 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); in soc15_pcie_wreg64()
226 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in soc15_uvd_ctx_rreg() argument
234 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
237 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
241 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_uvd_ctx_wreg() argument
248 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
251 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
254 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc15_didt_rreg() argument
262 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
265 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
269 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_didt_wreg() argument
276 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
279 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
282 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_gc_cac_rreg() argument
287 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
290 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
294 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_gc_cac_wreg() argument
298 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
301 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
304 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_se_cac_rreg() argument
309 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
312 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
316 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_se_cac_wreg() argument
320 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
323 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
326 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) in soc15_get_config_memsize() argument
328 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
331 static u32 soc15_get_xclk(struct amdgpu_device *adev) in soc15_get_xclk() argument
333 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
335 if (adev->asic_type == CHIP_RENOIR) in soc15_get_xclk()
337 if (adev->asic_type == CHIP_RAVEN) in soc15_get_xclk()
344 void soc15_grbm_select(struct amdgpu_device *adev, in soc15_grbm_select() argument
356 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) in soc15_vga_set_state() argument
361 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) in soc15_read_disabled_bios() argument
367 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, in soc15_read_bios_from_rom() argument
380 if (adev->flags & AMD_IS_APU) in soc15_read_bios_from_rom()
387 adev->smuio.funcs->get_rom_index_offset(adev); in soc15_read_bios_from_rom()
389 adev->smuio.funcs->get_rom_data_offset(adev); in soc15_read_bios_from_rom()
423 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
428 mutex_lock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
430 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
435 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in soc15_read_indexed_register()
436 mutex_unlock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
440 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, in soc15_get_register_value() argument
445 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
448 return adev->gfx.config.gb_addr_config; in soc15_get_register_value()
450 return adev->gfx.config.db_debug2; in soc15_get_register_value()
455 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
464 if (!adev->reg_offset[en->hwip][en->inst]) in soc15_read_register()
466 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
470 *value = soc15_get_register_value(adev, in soc15_read_register()
490 void soc15_program_register_sequence(struct amdgpu_device *adev, in soc15_program_register_sequence() argument
500 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
525 static int soc15_asic_baco_reset(struct amdgpu_device *adev) in soc15_asic_baco_reset() argument
527 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset()
531 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
532 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
534 ret = amdgpu_dpm_baco_reset(adev); in soc15_asic_baco_reset()
539 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
540 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
546 soc15_asic_reset_method(struct amdgpu_device *adev) in soc15_asic_reset_method() argument
550 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method()
552 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) in soc15_asic_reset_method()
566 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc15_asic_reset_method()
569 switch (adev->asic_type) { in soc15_asic_reset_method()
576 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
579 if (adev->psp.sos.fw_version >= 0x80067) in soc15_asic_reset_method()
580 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
586 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
587 adev->pm.fw_version <= 0x283400) in soc15_asic_reset_method()
608 static int soc15_asic_reset(struct amdgpu_device *adev) in soc15_asic_reset() argument
611 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || in soc15_asic_reset()
612 (adev->apu_flags & AMD_APU_IS_RAVEN2)) in soc15_asic_reset()
615 switch (soc15_asic_reset_method(adev)) { in soc15_asic_reset()
617 dev_info(adev->dev, "PCI reset\n"); in soc15_asic_reset()
618 return amdgpu_device_pci_reset(adev); in soc15_asic_reset()
620 dev_info(adev->dev, "BACO reset\n"); in soc15_asic_reset()
621 return soc15_asic_baco_reset(adev); in soc15_asic_reset()
623 dev_info(adev->dev, "MODE2 reset\n"); in soc15_asic_reset()
624 return amdgpu_dpm_mode2_reset(adev); in soc15_asic_reset()
626 dev_info(adev->dev, "MODE1 reset\n"); in soc15_asic_reset()
627 return amdgpu_device_mode1_reset(adev); in soc15_asic_reset()
631 static bool soc15_supports_baco(struct amdgpu_device *adev) in soc15_supports_baco() argument
633 switch (adev->asic_type) { in soc15_supports_baco()
637 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
639 if (adev->psp.sos.fw_version >= 0x80067) in soc15_supports_baco()
640 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
653 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc15_set_uvd_clocks() argument
666 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
673 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) in soc15_pcie_gen3_enable() argument
675 if (pci_is_root_bus(adev->pdev->bus)) in soc15_pcie_gen3_enable()
681 if (adev->flags & AMD_IS_APU) in soc15_pcie_gen3_enable()
684 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in soc15_pcie_gen3_enable()
691 static void soc15_program_aspm(struct amdgpu_device *adev) in soc15_program_aspm() argument
693 if (!amdgpu_device_should_use_aspm(adev)) in soc15_program_aspm()
696 if (!(adev->flags & AMD_IS_APU) && in soc15_program_aspm()
697 (adev->nbio.funcs->program_aspm)) in soc15_program_aspm()
698 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
701 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, in soc15_enable_doorbell_aperture() argument
704 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); in soc15_enable_doorbell_aperture()
705 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); in soc15_enable_doorbell_aperture()
717 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) in soc15_get_rev_id() argument
719 return adev->nbio.funcs->get_rev_id(adev); in soc15_get_rev_id()
722 static void soc15_reg_base_init(struct amdgpu_device *adev) in soc15_reg_base_init() argument
727 switch (adev->asic_type) { in soc15_reg_base_init()
731 vega10_reg_base_init(adev); in soc15_reg_base_init()
737 r = amdgpu_discovery_reg_base_init(adev); in soc15_reg_base_init()
743 vega10_reg_base_init(adev); in soc15_reg_base_init()
746 vega20_reg_base_init(adev); in soc15_reg_base_init()
749 arct_reg_base_init(adev); in soc15_reg_base_init()
752 aldebaran_reg_base_init(adev); in soc15_reg_base_init()
755 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); in soc15_reg_base_init()
760 void soc15_set_virt_ops(struct amdgpu_device *adev) in soc15_set_virt_ops() argument
762 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_virt_ops()
767 soc15_reg_base_init(adev); in soc15_set_virt_ops()
770 int soc15_set_ip_blocks(struct amdgpu_device *adev) in soc15_set_ip_blocks() argument
773 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
774 soc15_reg_base_init(adev); in soc15_set_ip_blocks()
776 if (adev->flags & AMD_IS_APU) { in soc15_set_ip_blocks()
777 adev->nbio.funcs = &nbio_v7_0_funcs; in soc15_set_ip_blocks()
778 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; in soc15_set_ip_blocks()
779 } else if (adev->asic_type == CHIP_VEGA20 || in soc15_set_ip_blocks()
780 adev->asic_type == CHIP_ARCTURUS || in soc15_set_ip_blocks()
781 adev->asic_type == CHIP_ALDEBARAN) { in soc15_set_ip_blocks()
782 adev->nbio.funcs = &nbio_v7_4_funcs; in soc15_set_ip_blocks()
783 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; in soc15_set_ip_blocks()
785 adev->nbio.funcs = &nbio_v6_1_funcs; in soc15_set_ip_blocks()
786 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; in soc15_set_ip_blocks()
788 adev->hdp.funcs = &hdp_v4_0_funcs; in soc15_set_ip_blocks()
790 if (adev->asic_type == CHIP_VEGA20 || in soc15_set_ip_blocks()
791 adev->asic_type == CHIP_ARCTURUS || in soc15_set_ip_blocks()
792 adev->asic_type == CHIP_ALDEBARAN) in soc15_set_ip_blocks()
793 adev->df.funcs = &df_v3_6_funcs; in soc15_set_ip_blocks()
795 adev->df.funcs = &df_v1_7_funcs; in soc15_set_ip_blocks()
797 if (adev->asic_type == CHIP_VEGA20 || in soc15_set_ip_blocks()
798 adev->asic_type == CHIP_ARCTURUS) in soc15_set_ip_blocks()
799 adev->smuio.funcs = &smuio_v11_0_funcs; in soc15_set_ip_blocks()
800 else if (adev->asic_type == CHIP_ALDEBARAN) in soc15_set_ip_blocks()
801 adev->smuio.funcs = &smuio_v13_0_funcs; in soc15_set_ip_blocks()
803 adev->smuio.funcs = &smuio_v9_0_funcs; in soc15_set_ip_blocks()
805 adev->rev_id = soc15_get_rev_id(adev); in soc15_set_ip_blocks()
807 switch (adev->asic_type) { in soc15_set_ip_blocks()
811 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
812 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
815 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
816 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { in soc15_set_ip_blocks()
817 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
818 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
820 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); in soc15_set_ip_blocks()
822 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
823 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); in soc15_set_ip_blocks()
825 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
827 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
828 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); in soc15_set_ip_blocks()
830 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
831 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { in soc15_set_ip_blocks()
832 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
833 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
835 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); in soc15_set_ip_blocks()
838 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
839 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
840 if (is_support_sw_smu(adev)) { in soc15_set_ip_blocks()
841 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
842 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in soc15_set_ip_blocks()
844 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in soc15_set_ip_blocks()
846 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
847 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in soc15_set_ip_blocks()
849 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
850 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
852 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { in soc15_set_ip_blocks()
853 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); in soc15_set_ip_blocks()
854 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); in soc15_set_ip_blocks()
858 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
859 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
860 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
861 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
862 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); in soc15_set_ip_blocks()
863 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
864 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
865 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in soc15_set_ip_blocks()
866 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
867 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in soc15_set_ip_blocks()
869 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
870 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
872 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); in soc15_set_ip_blocks()
875 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
876 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
878 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
879 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
880 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
881 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); in soc15_set_ip_blocks()
883 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); in soc15_set_ip_blocks()
884 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
885 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
888 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
889 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in soc15_set_ip_blocks()
890 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
891 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
892 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in soc15_set_ip_blocks()
894 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
895 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
896 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); in soc15_set_ip_blocks()
898 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); in soc15_set_ip_blocks()
900 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
901 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); in soc15_set_ip_blocks()
904 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
905 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
906 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
907 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
908 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); in soc15_set_ip_blocks()
909 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); in soc15_set_ip_blocks()
910 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
911 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
912 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
913 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in soc15_set_ip_blocks()
915 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
916 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
918 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in soc15_set_ip_blocks()
919 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); in soc15_set_ip_blocks()
922 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
923 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
925 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
926 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
927 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); in soc15_set_ip_blocks()
928 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); in soc15_set_ip_blocks()
930 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); in soc15_set_ip_blocks()
931 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
932 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); in soc15_set_ip_blocks()
935 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
936 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
938 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); in soc15_set_ip_blocks()
939 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); in soc15_set_ip_blocks()
940 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); in soc15_set_ip_blocks()
949 static bool soc15_need_full_reset(struct amdgpu_device *adev) in soc15_need_full_reset() argument
955 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in soc15_get_pcie_usage() argument
965 if (adev->flags & AMD_IS_APU) in soc15_get_pcie_usage()
1002 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vega20_get_pcie_usage() argument
1012 if (adev->flags & AMD_IS_APU) in vega20_get_pcie_usage()
1051 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) in soc15_need_reset_on_init() argument
1058 if (!amdgpu_passthrough(adev)) in soc15_need_reset_on_init()
1061 if (adev->flags & AMD_IS_APU) in soc15_need_reset_on_init()
1074 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) in soc15_get_pcie_replay_count() argument
1086 static void soc15_pre_asic_init(struct amdgpu_device *adev) in soc15_pre_asic_init() argument
1088 gmc_v9_0_restore_registers(adev); in soc15_pre_asic_init()
1138 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_early_init() local
1140 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in soc15_common_early_init()
1141 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in soc15_common_early_init()
1142 adev->smc_rreg = NULL; in soc15_common_early_init()
1143 adev->smc_wreg = NULL; in soc15_common_early_init()
1144 adev->pcie_rreg = &soc15_pcie_rreg; in soc15_common_early_init()
1145 adev->pcie_wreg = &soc15_pcie_wreg; in soc15_common_early_init()
1146 adev->pcie_rreg64 = &soc15_pcie_rreg64; in soc15_common_early_init()
1147 adev->pcie_wreg64 = &soc15_pcie_wreg64; in soc15_common_early_init()
1148 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; in soc15_common_early_init()
1149 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; in soc15_common_early_init()
1150 adev->didt_rreg = &soc15_didt_rreg; in soc15_common_early_init()
1151 adev->didt_wreg = &soc15_didt_wreg; in soc15_common_early_init()
1152 adev->gc_cac_rreg = &soc15_gc_cac_rreg; in soc15_common_early_init()
1153 adev->gc_cac_wreg = &soc15_gc_cac_wreg; in soc15_common_early_init()
1154 adev->se_cac_rreg = &soc15_se_cac_rreg; in soc15_common_early_init()
1155 adev->se_cac_wreg = &soc15_se_cac_wreg; in soc15_common_early_init()
1158 adev->external_rev_id = 0xFF; in soc15_common_early_init()
1159 switch (adev->asic_type) { in soc15_common_early_init()
1161 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1162 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1181 adev->pg_flags = 0; in soc15_common_early_init()
1182 adev->external_rev_id = 0x1; in soc15_common_early_init()
1185 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1186 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1204 adev->pg_flags = 0; in soc15_common_early_init()
1205 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1208 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1209 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1227 adev->pg_flags = 0; in soc15_common_early_init()
1228 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
1231 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1233 if (adev->rev_id >= 0x8) in soc15_common_early_init()
1234 adev->apu_flags |= AMD_APU_IS_RAVEN2; in soc15_common_early_init()
1236 if (adev->apu_flags & AMD_APU_IS_RAVEN2) in soc15_common_early_init()
1237 adev->external_rev_id = adev->rev_id + 0x79; in soc15_common_early_init()
1238 else if (adev->apu_flags & AMD_APU_IS_PICASSO) in soc15_common_early_init()
1239 adev->external_rev_id = adev->rev_id + 0x41; in soc15_common_early_init()
1240 else if (adev->rev_id == 1) in soc15_common_early_init()
1241 adev->external_rev_id = adev->rev_id + 0x20; in soc15_common_early_init()
1243 adev->external_rev_id = adev->rev_id + 0x01; in soc15_common_early_init()
1245 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { in soc15_common_early_init()
1246 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1261 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1262 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { in soc15_common_early_init()
1263 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1281 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1284 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1303 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1307 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1308 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1322 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1323 adev->external_rev_id = adev->rev_id + 0x32; in soc15_common_early_init()
1326 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1328 if (adev->apu_flags & AMD_APU_IS_RENOIR) in soc15_common_early_init()
1329 adev->external_rev_id = adev->rev_id + 0x91; in soc15_common_early_init()
1331 adev->external_rev_id = adev->rev_id + 0xa1; in soc15_common_early_init()
1332 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1351 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1357 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1358 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1366 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1367 adev->external_rev_id = adev->rev_id + 0x3c; in soc15_common_early_init()
1374 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1375 amdgpu_virt_init_setting(adev); in soc15_common_early_init()
1376 xgpu_ai_mailbox_set_irq_funcs(adev); in soc15_common_early_init()
1384 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_late_init() local
1387 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1388 xgpu_ai_mailbox_get_irq(adev); in soc15_common_late_init()
1390 if (adev->nbio.ras_funcs && in soc15_common_late_init()
1391 adev->nbio.ras_funcs->ras_late_init) in soc15_common_late_init()
1392 r = adev->nbio.ras_funcs->ras_late_init(adev); in soc15_common_late_init()
1399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_init() local
1401 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1402 xgpu_ai_mailbox_add_irq_id(adev); in soc15_common_sw_init()
1404 adev->df.funcs->sw_init(adev); in soc15_common_sw_init()
1411 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_fini() local
1413 if (adev->nbio.ras_funcs && in soc15_common_sw_fini()
1414 adev->nbio.ras_funcs->ras_fini) in soc15_common_sw_fini()
1415 adev->nbio.ras_funcs->ras_fini(adev); in soc15_common_sw_fini()
1416 adev->df.funcs->sw_fini(adev); in soc15_common_sw_fini()
1420 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) in soc15_sdma_doorbell_range_init() argument
1425 if (!amdgpu_sriov_vf(adev)) { in soc15_sdma_doorbell_range_init()
1426 for (i = 0; i < adev->sdma.num_instances; i++) { in soc15_sdma_doorbell_range_init()
1427 adev->nbio.funcs->sdma_doorbell_range(adev, i, in soc15_sdma_doorbell_range_init()
1428 true, adev->doorbell_index.sdma_engine[i] << 1, in soc15_sdma_doorbell_range_init()
1429 adev->doorbell_index.sdma_doorbell_range); in soc15_sdma_doorbell_range_init()
1436 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_init() local
1439 soc15_pcie_gen3_enable(adev); in soc15_common_hw_init()
1441 soc15_program_aspm(adev); in soc15_common_hw_init()
1443 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1448 if (adev->nbio.funcs->remap_hdp_registers) in soc15_common_hw_init()
1449 adev->nbio.funcs->remap_hdp_registers(adev); in soc15_common_hw_init()
1452 soc15_enable_doorbell_aperture(adev, true); in soc15_common_hw_init()
1459 soc15_sdma_doorbell_range_init(adev); in soc15_common_hw_init()
1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_fini() local
1469 soc15_enable_doorbell_aperture(adev, false); in soc15_common_hw_fini()
1470 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1471 xgpu_ai_mailbox_put_irq(adev); in soc15_common_hw_fini()
1473 if (adev->nbio.ras_if && in soc15_common_hw_fini()
1474 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { in soc15_common_hw_fini()
1475 if (adev->nbio.ras_funcs && in soc15_common_hw_fini()
1476 adev->nbio.ras_funcs->init_ras_controller_interrupt) in soc15_common_hw_fini()
1477 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); in soc15_common_hw_fini()
1478 if (adev->nbio.ras_funcs && in soc15_common_hw_fini()
1479 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
1480 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc15_common_hw_fini()
1488 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_suspend() local
1490 return soc15_common_hw_fini(adev); in soc15_common_suspend()
1495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_resume() local
1497 return soc15_common_hw_init(adev); in soc15_common_resume()
1515 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) in soc15_update_drm_clock_gating() argument
1521 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) in soc15_update_drm_clock_gating()
1544 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_drm_light_sleep() argument
1550 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in soc15_update_drm_light_sleep()
1562 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_set_clockgating_state() local
1564 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1567 switch (adev->asic_type) { in soc15_common_set_clockgating_state()
1571 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1573 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1575 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1577 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1579 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1581 adev->smuio.funcs->update_rom_clock_gating(adev, in soc15_common_set_clockgating_state()
1583 adev->df.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1588 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1590 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1592 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1594 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1596 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1601 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1612 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_get_clockgating_state() local
1615 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
1618 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1619 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()
1621 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1622 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1624 if (adev->asic_type != CHIP_ALDEBARAN) { in soc15_common_get_clockgating_state()
1638 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1639 adev->smuio.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1641 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1642 adev->df.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()