28 #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)  argument
40 #define WREG32_FIELD15(ip, idx, reg, field, val)	\  argument
41 	 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
43 					adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
44 					0, ip##_HWIP) & \
46 			      0, ip##_HWIP)
48 #define RREG32_SOC15(ip, inst, reg) \  argument
49 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
50 			 0, ip##_HWIP)
52 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)  argument
54 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \  argument
55 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
56 			 AMDGPU_REGS_NO_KIQ, ip##_HWIP)
58 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \  argument
59 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_H…
61 #define WREG32_SOC15(ip, inst, reg, value) \  argument
62 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
63 			  value, 0, ip##_HWIP)
65 #define WREG32_SOC15_IP(ip, reg, value) \  argument
66 	 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
68 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \  argument
69 	__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
70 			     value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
72 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \  argument
73 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
74 			  value, 0, ip##_HWIP)
76 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \  argument
80 		uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
89 			tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
130 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \  argument
131 …__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS…
143 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \  argument
145 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
161 #define RREG32_SOC15_RLC(ip, inst, reg) \  argument
162 …__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip#…
164 #define WREG32_SOC15_RLC(ip, inst, reg, value) \  argument
166 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
167 		__WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \
170 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \  argument
176 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \  argument
177 	__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
178 			     (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
179 						   AMDGPU_REGS_RLC, ip##_HWIP) & \
181 			     AMDGPU_REGS_RLC, ip##_HWIP)
183 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \  argument
184 …_WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMD…
186 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \  argument
187 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_RE…