1434 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_insert_start()
1437 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_insert_start()
1453 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_insert_end()
1475 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));  in vcn_v1_0_dec_ring_emit_fence()
1478 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_fence()
1481 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_fence()
1484 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_fence()
1488 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_fence()
1491 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_fence()
1494 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_fence()
1517 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));  in vcn_v1_0_dec_ring_emit_ib()
1521 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));  in vcn_v1_0_dec_ring_emit_ib()
1524 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));  in vcn_v1_0_dec_ring_emit_ib()
1527 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));  in vcn_v1_0_dec_ring_emit_ib()
1538 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_reg_wait()
1541 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_reg_wait()
1544 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));  in vcn_v1_0_dec_ring_emit_reg_wait()
1547 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_reg_wait()
1572 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_wreg()
1575 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_wreg()
1578 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_wreg()
1758 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));  in vcn_v1_0_dec_ring_insert_nop()