316 			lower_32_bits(adev->vcn.inst->gpu_addr));  in vcn_v1_0_mc_resume_spg_mode()
318 			upper_32_bits(adev->vcn.inst->gpu_addr));  in vcn_v1_0_mc_resume_spg_mode()
328 		     lower_32_bits(adev->vcn.inst->gpu_addr + offset));  in vcn_v1_0_mc_resume_spg_mode()
330 		     upper_32_bits(adev->vcn.inst->gpu_addr + offset));  in vcn_v1_0_mc_resume_spg_mode()
336 		     lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));  in vcn_v1_0_mc_resume_spg_mode()
338 		     upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));  in vcn_v1_0_mc_resume_spg_mode()
386 			lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);  in vcn_v1_0_mc_resume_dpg_mode()
388 			upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);  in vcn_v1_0_mc_resume_dpg_mode()
398 		     lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);  in vcn_v1_0_mc_resume_dpg_mode()
400 		     upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);  in vcn_v1_0_mc_resume_dpg_mode()
408 		     lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),  in vcn_v1_0_mc_resume_dpg_mode()
411 		     upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),  in vcn_v1_0_mc_resume_dpg_mode()
920 			(upper_32_bits(ring->gpu_addr) >> 2));  in vcn_v1_0_start_spg_mode()
924 			lower_32_bits(ring->gpu_addr));  in vcn_v1_0_start_spg_mode()
926 			upper_32_bits(ring->gpu_addr));  in vcn_v1_0_start_spg_mode()
943 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v1_0_start_spg_mode()
944 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v1_0_start_spg_mode()
950 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);  in vcn_v1_0_start_spg_mode()
951 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vcn_v1_0_start_spg_mode()
1078 								(upper_32_bits(ring->gpu_addr) >> 2));  in vcn_v1_0_start_dpg_mode()
1082 								lower_32_bits(ring->gpu_addr));  in vcn_v1_0_start_dpg_mode()
1084 								upper_32_bits(ring->gpu_addr));  in vcn_v1_0_start_dpg_mode()
1248 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v1_0_pause_dpg_mode()
1249 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v1_0_pause_dpg_mode()
1255 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);  in vcn_v1_0_pause_dpg_mode()
1256 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vcn_v1_0_pause_dpg_mode()
1314 							lower_32_bits(ring->gpu_addr));  in vcn_v1_0_pause_dpg_mode()
1316 							upper_32_bits(ring->gpu_addr));  in vcn_v1_0_pause_dpg_mode()
1522 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));  in vcn_v1_0_dec_ring_emit_ib()
1525 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in vcn_v1_0_dec_ring_emit_ib()
1681 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));  in vcn_v1_0_enc_ring_emit_ib()
1682 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in vcn_v1_0_enc_ring_emit_ib()