Lines Matching refs:m
47 struct v10_compute_mqd *m; in update_cu_mask() local
56 m = get_mqd(mqd); in update_cu_mask()
57 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
58 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
59 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
60 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
63 m->compute_static_thread_mgmt_se0, in update_cu_mask()
64 m->compute_static_thread_mgmt_se1, in update_cu_mask()
65 m->compute_static_thread_mgmt_se2, in update_cu_mask()
66 m->compute_static_thread_mgmt_se3); in update_cu_mask()
69 static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) in set_priority() argument
71 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; in set_priority()
72 m->cp_hqd_queue_priority = q->priority; in set_priority()
92 struct v10_compute_mqd *m; in init_mqd() local
94 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; in init_mqd()
97 memset(m, 0, sizeof(struct v10_compute_mqd)); in init_mqd()
99 m->header = 0xC0310800; in init_mqd()
100 m->compute_pipelinestat_enable = 1; in init_mqd()
101 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; in init_mqd()
102 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; in init_mqd()
103 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; in init_mqd()
104 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; in init_mqd()
106 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | in init_mqd()
109 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; in init_mqd()
111 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
112 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
114 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | in init_mqd()
119 m->cp_hqd_aql_control = in init_mqd()
124 m->cp_hqd_persistent_state |= in init_mqd()
126 m->cp_hqd_ctx_save_base_addr_lo = in init_mqd()
128 m->cp_hqd_ctx_save_base_addr_hi = in init_mqd()
130 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; in init_mqd()
131 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; in init_mqd()
132 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; in init_mqd()
133 m->cp_hqd_wg_state_offset = q->ctl_stack_size; in init_mqd()
136 *mqd = m; in init_mqd()
139 mm->update_mqd(mm, m, q); in init_mqd()
167 struct v10_compute_mqd *m; in update_mqd() local
169 m = get_mqd(mqd); in update_mqd()
171 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
172 m->cp_hqd_pq_control |= in update_mqd()
174 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
176 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
177 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
179 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
180 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
181 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
182 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
184 m->cp_hqd_pq_doorbell_control = in update_mqd()
188 m->cp_hqd_pq_doorbell_control); in update_mqd()
190 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; in update_mqd()
199 m->cp_hqd_eop_control = min(0xA, in update_mqd()
201 m->cp_hqd_eop_base_addr_lo = in update_mqd()
203 m->cp_hqd_eop_base_addr_hi = in update_mqd()
206 m->cp_hqd_iq_timer = 0; in update_mqd()
208 m->cp_hqd_vmid = q->vmid; in update_mqd()
212 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
215 m->cp_hqd_pq_doorbell_control |= in update_mqd()
219 m->cp_hqd_ctx_save_control = 0; in update_mqd()
222 set_priority(m, q); in update_mqd()
229 struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd; in read_doorbell_id() local
231 return m->queue_doorbell_id0; in read_doorbell_id()
264 struct v10_compute_mqd *m; in get_wave_state() local
266 m = get_mqd(mqd); in get_wave_state()
273 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - in get_wave_state()
274 m->cp_hqd_cntl_stack_offset; in get_wave_state()
275 *save_area_used_size = m->cp_hqd_wg_state_offset - in get_wave_state()
276 m->cp_hqd_cntl_stack_size; in get_wave_state()
290 struct v10_compute_mqd *m; in init_mqd_hiq() local
294 m = get_mqd(*mqd); in init_mqd_hiq()
296 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
304 struct v10_sdma_mqd *m; in init_mqd_sdma() local
306 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; in init_mqd_sdma()
308 memset(m, 0, sizeof(struct v10_sdma_mqd)); in init_mqd_sdma()
310 *mqd = m; in init_mqd_sdma()
314 mm->update_mqd(mm, m, q); in init_mqd_sdma()
331 struct v10_sdma_mqd *m; in update_mqd_sdma() local
333 m = get_sdma_mqd(mqd); in update_mqd_sdma()
334 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) in update_mqd_sdma()
340 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
341 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
342 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
343 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
344 m->sdmax_rlcx_doorbell_offset = in update_mqd_sdma()
347 m->sdma_engine_id = q->sdma_engine_id; in update_mqd_sdma()
348 m->sdma_queue_id = q->sdma_queue_id; in update_mqd_sdma()
349 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; in update_mqd_sdma()
375 static int debugfs_show_mqd(struct seq_file *m, void *data) in debugfs_show_mqd() argument
377 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, in debugfs_show_mqd()
382 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) in debugfs_show_mqd_sdma() argument
384 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, in debugfs_show_mqd_sdma()