Lines Matching refs:SF
64 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
65 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
66 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
67 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
68 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
69 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
70 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
71 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
72 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
73 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
74 SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
75 SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
76 SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
77 SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
78 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\
79 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\
80 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\
81 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
82 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
83 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\
84 SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
85 SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh)