Lines Matching refs:adev
110 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, in amdgpu_dpm_print_ps_status() argument
114 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
116 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
118 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
123 void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev) in amdgpu_dpm_get_active_displays() argument
125 struct drm_device *ddev = adev_to_drm(adev); in amdgpu_dpm_get_active_displays()
129 adev->pm.dpm.new_active_crtcs = 0; in amdgpu_dpm_get_active_displays()
130 adev->pm.dpm.new_active_crtc_count = 0; in amdgpu_dpm_get_active_displays()
131 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { in amdgpu_dpm_get_active_displays()
136 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); in amdgpu_dpm_get_active_displays()
137 adev->pm.dpm.new_active_crtc_count++; in amdgpu_dpm_get_active_displays()
144 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev) in amdgpu_dpm_get_vblank_time() argument
146 struct drm_device *dev = adev_to_drm(adev); in amdgpu_dpm_get_vblank_time()
152 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { in amdgpu_dpm_get_vblank_time()
171 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) in amdgpu_dpm_get_vrefresh() argument
173 struct drm_device *dev = adev_to_drm(adev); in amdgpu_dpm_get_vrefresh()
178 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { in amdgpu_dpm_get_vrefresh()
256 int amdgpu_get_platform_caps(struct amdgpu_device *adev) in amdgpu_get_platform_caps() argument
258 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_get_platform_caps()
269 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in amdgpu_get_platform_caps()
270 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in amdgpu_get_platform_caps()
271 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in amdgpu_get_platform_caps()
286 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) in amdgpu_parse_extended_power_table() argument
288 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_parse_extended_power_table()
308 adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in amdgpu_parse_extended_power_table()
309 adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in amdgpu_parse_extended_power_table()
310 adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); in amdgpu_parse_extended_power_table()
311 adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); in amdgpu_parse_extended_power_table()
312 adev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin); in amdgpu_parse_extended_power_table()
313 adev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed); in amdgpu_parse_extended_power_table()
314 adev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh); in amdgpu_parse_extended_power_table()
316 adev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax); in amdgpu_parse_extended_power_table()
318 adev->pm.dpm.fan.t_max = 10900; in amdgpu_parse_extended_power_table()
319 adev->pm.dpm.fan.cycle_delay = 100000; in amdgpu_parse_extended_power_table()
321 adev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode; in amdgpu_parse_extended_power_table()
322 adev->pm.dpm.fan.default_max_fan_pwm = in amdgpu_parse_extended_power_table()
324 adev->pm.dpm.fan.default_fan_output_sensitivity = 4836; in amdgpu_parse_extended_power_table()
325 adev->pm.dpm.fan.fan_output_sensitivity = in amdgpu_parse_extended_power_table()
328 adev->pm.dpm.fan.ucode_fan_control = true; in amdgpu_parse_extended_power_table()
339 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
342 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
350 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in amdgpu_parse_extended_power_table()
353 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
361 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in amdgpu_parse_extended_power_table()
364 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
372 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in amdgpu_parse_extended_power_table()
375 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
385 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in amdgpu_parse_extended_power_table()
388 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in amdgpu_parse_extended_power_table()
391 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in amdgpu_parse_extended_power_table()
393 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in amdgpu_parse_extended_power_table()
404 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = in amdgpu_parse_extended_power_table()
408 if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { in amdgpu_parse_extended_power_table()
409 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
415 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = in amdgpu_parse_extended_power_table()
417 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = in amdgpu_parse_extended_power_table()
419 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = in amdgpu_parse_extended_power_table()
424 adev->pm.dpm.dyn_state.phase_shedding_limits_table.count = in amdgpu_parse_extended_power_table()
432 adev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); in amdgpu_parse_extended_power_table()
433 adev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); in amdgpu_parse_extended_power_table()
434 adev->pm.dpm.near_tdp_limit_adjusted = adev->pm.dpm.near_tdp_limit; in amdgpu_parse_extended_power_table()
435 adev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); in amdgpu_parse_extended_power_table()
436 if (adev->pm.dpm.tdp_od_limit) in amdgpu_parse_extended_power_table()
437 adev->pm.dpm.power_control = true; in amdgpu_parse_extended_power_table()
439 adev->pm.dpm.power_control = false; in amdgpu_parse_extended_power_table()
440 adev->pm.dpm.tdp_adjustment = 0; in amdgpu_parse_extended_power_table()
441 adev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold); in amdgpu_parse_extended_power_table()
442 adev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage); in amdgpu_parse_extended_power_table()
443 adev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope); in amdgpu_parse_extended_power_table()
451 adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); in amdgpu_parse_extended_power_table()
452 if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) { in amdgpu_parse_extended_power_table()
453 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
458 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in amdgpu_parse_extended_power_table()
459 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = in amdgpu_parse_extended_power_table()
461 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = in amdgpu_parse_extended_power_table()
463 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = in amdgpu_parse_extended_power_table()
466 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = in amdgpu_parse_extended_power_table()
468 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = in amdgpu_parse_extended_power_table()
474 adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; in amdgpu_parse_extended_power_table()
505 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
507 if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
508 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
511 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
519 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in amdgpu_parse_extended_power_table()
521 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in amdgpu_parse_extended_power_table()
523 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
528 adev->pm.dpm.num_of_vce_states = in amdgpu_parse_extended_power_table()
531 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in amdgpu_parse_extended_power_table()
535 adev->pm.dpm.vce_states[i].evclk = in amdgpu_parse_extended_power_table()
537 adev->pm.dpm.vce_states[i].ecclk = in amdgpu_parse_extended_power_table()
539 adev->pm.dpm.vce_states[i].clk_idx = in amdgpu_parse_extended_power_table()
541 adev->pm.dpm.vce_states[i].pstate = in amdgpu_parse_extended_power_table()
560 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
562 if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
563 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
566 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
573 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = in amdgpu_parse_extended_power_table()
575 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = in amdgpu_parse_extended_power_table()
577 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
592 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
594 if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
595 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
598 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
602 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
604 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
615 adev->pm.dpm.dyn_state.ppm_table = in amdgpu_parse_extended_power_table()
617 if (!adev->pm.dpm.dyn_state.ppm_table) { in amdgpu_parse_extended_power_table()
618 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
621 adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; in amdgpu_parse_extended_power_table()
622 adev->pm.dpm.dyn_state.ppm_table->cpu_core_number = in amdgpu_parse_extended_power_table()
624 adev->pm.dpm.dyn_state.ppm_table->platform_tdp = in amdgpu_parse_extended_power_table()
626 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = in amdgpu_parse_extended_power_table()
628 adev->pm.dpm.dyn_state.ppm_table->platform_tdc = in amdgpu_parse_extended_power_table()
630 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = in amdgpu_parse_extended_power_table()
632 adev->pm.dpm.dyn_state.ppm_table->apu_tdp = in amdgpu_parse_extended_power_table()
634 adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in amdgpu_parse_extended_power_table()
636 adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = in amdgpu_parse_extended_power_table()
638 adev->pm.dpm.dyn_state.ppm_table->tj_max = in amdgpu_parse_extended_power_table()
650 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
652 if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
653 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
656 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
660 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
662 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
673 adev->pm.dpm.dyn_state.cac_tdp_table = in amdgpu_parse_extended_power_table()
675 if (!adev->pm.dpm.dyn_state.cac_tdp_table) { in amdgpu_parse_extended_power_table()
676 amdgpu_free_extended_power_table(adev); in amdgpu_parse_extended_power_table()
683 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = in amdgpu_parse_extended_power_table()
690 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; in amdgpu_parse_extended_power_table()
693 adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); in amdgpu_parse_extended_power_table()
694 adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = in amdgpu_parse_extended_power_table()
696 adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); in amdgpu_parse_extended_power_table()
697 adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = in amdgpu_parse_extended_power_table()
699 adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = in amdgpu_parse_extended_power_table()
701 adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = in amdgpu_parse_extended_power_table()
703 adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = in amdgpu_parse_extended_power_table()
712 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk, in amdgpu_parse_extended_power_table()
715 kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries); in amdgpu_parse_extended_power_table()
724 void amdgpu_free_extended_power_table(struct amdgpu_device *adev) in amdgpu_free_extended_power_table() argument
726 struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; in amdgpu_free_extended_power_table()
766 void amdgpu_add_thermal_controller(struct amdgpu_device *adev) in amdgpu_add_thermal_controller() argument
768 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_add_thermal_controller()
786 adev->pm.no_fan = true; in amdgpu_add_thermal_controller()
787 adev->pm.fan_pulses_per_revolution = in amdgpu_add_thermal_controller()
789 if (adev->pm.fan_pulses_per_revolution) { in amdgpu_add_thermal_controller()
790 adev->pm.fan_min_rpm = controller->ucFanMinRPM; in amdgpu_add_thermal_controller()
791 adev->pm.fan_max_rpm = controller->ucFanMaxRPM; in amdgpu_add_thermal_controller()
797 adev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; in amdgpu_add_thermal_controller()
802 adev->pm.int_thermal_type = THERMAL_TYPE_RV770; in amdgpu_add_thermal_controller()
807 adev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; in amdgpu_add_thermal_controller()
812 adev->pm.int_thermal_type = THERMAL_TYPE_SUMO; in amdgpu_add_thermal_controller()
817 adev->pm.int_thermal_type = THERMAL_TYPE_NI; in amdgpu_add_thermal_controller()
822 adev->pm.int_thermal_type = THERMAL_TYPE_SI; in amdgpu_add_thermal_controller()
827 adev->pm.int_thermal_type = THERMAL_TYPE_CI; in amdgpu_add_thermal_controller()
832 adev->pm.int_thermal_type = THERMAL_TYPE_KV; in amdgpu_add_thermal_controller()
837 adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; in amdgpu_add_thermal_controller()
843 adev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; in amdgpu_add_thermal_controller()
849 adev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; in amdgpu_add_thermal_controller()
856 adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; in amdgpu_add_thermal_controller()
857 i2c_bus = amdgpu_atombios_lookup_i2c_gpio(adev, controller->ucI2cLine); in amdgpu_add_thermal_controller()
858 adev->pm.i2c_bus = amdgpu_i2c_lookup(adev, &i2c_bus); in amdgpu_add_thermal_controller()
859 if (adev->pm.i2c_bus) { in amdgpu_add_thermal_controller()
864 i2c_new_client_device(&adev->pm.i2c_bus->adapter, &info); in amdgpu_add_thermal_controller()
876 enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev, in amdgpu_get_pcie_gen_support() argument
904 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in amdgpu_get_vce_clock_state() local
906 if (idx < adev->pm.dpm.num_of_vce_states) in amdgpu_get_vce_clock_state()
907 return &adev->pm.dpm.vce_states[idx]; in amdgpu_get_vce_clock_state()
912 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_sclk() argument
914 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk()
916 return pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low)); in amdgpu_dpm_get_sclk()
919 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_mclk() argument
921 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk()
923 return pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low)); in amdgpu_dpm_get_mclk()
926 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) in amdgpu_dpm_set_powergating_by_smu() argument
929 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_powergating_by_smu()
932 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { in amdgpu_dpm_set_powergating_by_smu()
933 dev_dbg(adev->dev, "IP block%d already in the target %s state!", in amdgpu_dpm_set_powergating_by_smu()
968 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
970 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
971 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
982 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
990 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); in amdgpu_dpm_set_powergating_by_smu()
995 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) in amdgpu_dpm_baco_enter() argument
997 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_enter()
998 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_enter()
1010 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) in amdgpu_dpm_baco_exit() argument
1012 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_exit()
1013 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_exit()
1025 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, in amdgpu_dpm_set_mp1_state() argument
1029 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_mp1_state()
1033 adev->powerplay.pp_handle, in amdgpu_dpm_set_mp1_state()
1040 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_baco_supported() argument
1042 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_is_baco_supported()
1043 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_is_baco_supported()
1057 if (adev->in_s3) in amdgpu_dpm_is_baco_supported()
1066 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode2_reset() argument
1068 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_mode2_reset()
1069 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_mode2_reset()
1077 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) in amdgpu_dpm_baco_reset() argument
1079 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_reset()
1080 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_reset()
1099 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_mode1_reset_supported() argument
1101 struct smu_context *smu = &adev->smu; in amdgpu_dpm_is_mode1_reset_supported()
1103 if (is_support_sw_smu(adev)) in amdgpu_dpm_is_mode1_reset_supported()
1109 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode1_reset() argument
1111 struct smu_context *smu = &adev->smu; in amdgpu_dpm_mode1_reset()
1113 if (is_support_sw_smu(adev)) in amdgpu_dpm_mode1_reset()
1119 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, in amdgpu_dpm_switch_power_profile() argument
1123 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_switch_power_profile()
1126 if (amdgpu_sriov_vf(adev)) in amdgpu_dpm_switch_power_profile()
1131 adev->powerplay.pp_handle, type, en); in amdgpu_dpm_switch_power_profile()
1136 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, in amdgpu_dpm_set_xgmi_pstate() argument
1139 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_xgmi_pstate()
1143 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, in amdgpu_dpm_set_xgmi_pstate()
1149 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, in amdgpu_dpm_set_df_cstate() argument
1153 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_df_cstate()
1154 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_df_cstate()
1162 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) in amdgpu_dpm_allow_xgmi_power_down() argument
1164 struct smu_context *smu = &adev->smu; in amdgpu_dpm_allow_xgmi_power_down()
1166 if (is_support_sw_smu(adev)) in amdgpu_dpm_allow_xgmi_power_down()
1172 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) in amdgpu_dpm_enable_mgpu_fan_boost() argument
1174 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_mgpu_fan_boost()
1176 adev->powerplay.pp_funcs; in amdgpu_dpm_enable_mgpu_fan_boost()
1185 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, in amdgpu_dpm_set_clockgating_by_smu() argument
1188 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_clockgating_by_smu()
1190 adev->powerplay.pp_funcs; in amdgpu_dpm_set_clockgating_by_smu()
1200 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, in amdgpu_dpm_smu_i2c_bus_access() argument
1203 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_smu_i2c_bus_access()
1205 adev->powerplay.pp_funcs; in amdgpu_dpm_smu_i2c_bus_access()
1215 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) in amdgpu_pm_acpi_event_handler() argument
1217 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
1218 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
1220 adev->pm.ac_power = true; in amdgpu_pm_acpi_event_handler()
1222 adev->pm.ac_power = false; in amdgpu_pm_acpi_event_handler()
1223 if (adev->powerplay.pp_funcs && in amdgpu_pm_acpi_event_handler()
1224 adev->powerplay.pp_funcs->enable_bapm) in amdgpu_pm_acpi_event_handler()
1225 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
1226 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
1228 if (is_support_sw_smu(adev)) in amdgpu_pm_acpi_event_handler()
1229 smu_set_ac_dc(&adev->smu); in amdgpu_pm_acpi_event_handler()
1233 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, in amdgpu_dpm_read_sensor() argument
1236 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_read_sensor()
1243 ret = pp_funcs->read_sensor((adev)->powerplay.pp_handle, in amdgpu_dpm_read_sensor()
1253 struct amdgpu_device *adev = in amdgpu_dpm_thermal_work_handler() local
1260 if (!adev->pm.dpm_enabled) in amdgpu_dpm_thermal_work_handler()
1263 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, in amdgpu_dpm_thermal_work_handler()
1265 if (temp < adev->pm.dpm.thermal.min_temp) in amdgpu_dpm_thermal_work_handler()
1267 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1269 if (adev->pm.dpm.thermal.high_to_low) in amdgpu_dpm_thermal_work_handler()
1271 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1273 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_thermal_work_handler()
1275 adev->pm.dpm.thermal_active = true; in amdgpu_dpm_thermal_work_handler()
1277 adev->pm.dpm.thermal_active = false; in amdgpu_dpm_thermal_work_handler()
1278 adev->pm.dpm.state = dpm_state; in amdgpu_dpm_thermal_work_handler()
1279 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_thermal_work_handler()
1281 amdgpu_pm_compute_clocks(adev); in amdgpu_dpm_thermal_work_handler()
1284 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev, in amdgpu_dpm_pick_power_state() argument
1290 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? in amdgpu_dpm_pick_power_state()
1294 if (single_display && adev->powerplay.pp_funcs->vblank_too_short) { in amdgpu_dpm_pick_power_state()
1295 if (amdgpu_dpm_vblank_too_short(adev)) in amdgpu_dpm_pick_power_state()
1310 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in amdgpu_dpm_pick_power_state()
1311 ps = &adev->pm.dpm.ps[i]; in amdgpu_dpm_pick_power_state()
1344 if (adev->pm.dpm.uvd_ps) in amdgpu_dpm_pick_power_state()
1345 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
1365 return adev->pm.dpm.boot_ps; in amdgpu_dpm_pick_power_state()
1394 if (adev->pm.dpm.uvd_ps) { in amdgpu_dpm_pick_power_state()
1395 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
1418 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) in amdgpu_dpm_change_power_state_locked() argument
1426 if (!adev->pm.dpm_enabled) in amdgpu_dpm_change_power_state_locked()
1429 if (adev->pm.dpm.user_state != adev->pm.dpm.state) { in amdgpu_dpm_change_power_state_locked()
1431 if ((!adev->pm.dpm.thermal_active) && in amdgpu_dpm_change_power_state_locked()
1432 (!adev->pm.dpm.uvd_active)) in amdgpu_dpm_change_power_state_locked()
1433 adev->pm.dpm.state = adev->pm.dpm.user_state; in amdgpu_dpm_change_power_state_locked()
1435 dpm_state = adev->pm.dpm.state; in amdgpu_dpm_change_power_state_locked()
1437 ps = amdgpu_dpm_pick_power_state(adev, dpm_state); in amdgpu_dpm_change_power_state_locked()
1439 adev->pm.dpm.requested_ps = ps; in amdgpu_dpm_change_power_state_locked()
1443 if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) { in amdgpu_dpm_change_power_state_locked()
1445 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); in amdgpu_dpm_change_power_state_locked()
1447 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); in amdgpu_dpm_change_power_state_locked()
1451 ps->vce_active = adev->pm.dpm.vce_active; in amdgpu_dpm_change_power_state_locked()
1452 if (adev->powerplay.pp_funcs->display_configuration_changed) in amdgpu_dpm_change_power_state_locked()
1453 amdgpu_dpm_display_configuration_changed(adev); in amdgpu_dpm_change_power_state_locked()
1455 ret = amdgpu_dpm_pre_set_power_state(adev); in amdgpu_dpm_change_power_state_locked()
1459 if (adev->powerplay.pp_funcs->check_state_equal) { in amdgpu_dpm_change_power_state_locked()
1460 …if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &e… in amdgpu_dpm_change_power_state_locked()
1467 amdgpu_dpm_set_power_state(adev); in amdgpu_dpm_change_power_state_locked()
1468 amdgpu_dpm_post_set_power_state(adev); in amdgpu_dpm_change_power_state_locked()
1470 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; in amdgpu_dpm_change_power_state_locked()
1471 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; in amdgpu_dpm_change_power_state_locked()
1473 if (adev->powerplay.pp_funcs->force_performance_level) { in amdgpu_dpm_change_power_state_locked()
1474 if (adev->pm.dpm.thermal_active) { in amdgpu_dpm_change_power_state_locked()
1475 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; in amdgpu_dpm_change_power_state_locked()
1477 amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW); in amdgpu_dpm_change_power_state_locked()
1479 adev->pm.dpm.forced_level = level; in amdgpu_dpm_change_power_state_locked()
1482 amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level); in amdgpu_dpm_change_power_state_locked()
1487 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) in amdgpu_pm_compute_clocks() argument
1491 if (!adev->pm.dpm_enabled) in amdgpu_pm_compute_clocks()
1494 if (adev->mode_info.num_crtc) in amdgpu_pm_compute_clocks()
1495 amdgpu_display_bandwidth_update(adev); in amdgpu_pm_compute_clocks()
1498 struct amdgpu_ring *ring = adev->rings[i]; in amdgpu_pm_compute_clocks()
1503 if (adev->powerplay.pp_funcs->dispatch_tasks) { in amdgpu_pm_compute_clocks()
1504 if (!amdgpu_device_has_dc_support(adev)) { in amdgpu_pm_compute_clocks()
1505 mutex_lock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1506 amdgpu_dpm_get_active_displays(adev); in amdgpu_pm_compute_clocks()
1507 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count; in amdgpu_pm_compute_clocks()
1508 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev); in amdgpu_pm_compute_clocks()
1509 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev); in amdgpu_pm_compute_clocks()
1513 if (adev->pm.pm_display_cfg.vrefresh > 120) in amdgpu_pm_compute_clocks()
1514 adev->pm.pm_display_cfg.min_vblank_time = 0; in amdgpu_pm_compute_clocks()
1515 if (adev->powerplay.pp_funcs->display_configuration_change) in amdgpu_pm_compute_clocks()
1516 adev->powerplay.pp_funcs->display_configuration_change( in amdgpu_pm_compute_clocks()
1517 adev->powerplay.pp_handle, in amdgpu_pm_compute_clocks()
1518 &adev->pm.pm_display_cfg); in amdgpu_pm_compute_clocks()
1519 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1521 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL); in amdgpu_pm_compute_clocks()
1523 mutex_lock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1524 amdgpu_dpm_get_active_displays(adev); in amdgpu_pm_compute_clocks()
1525 amdgpu_dpm_change_power_state_locked(adev); in amdgpu_pm_compute_clocks()
1526 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1530 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_uvd() argument
1534 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_uvd()
1535 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
1537 adev->pm.dpm.uvd_active = true; in amdgpu_dpm_enable_uvd()
1538 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; in amdgpu_dpm_enable_uvd()
1540 adev->pm.dpm.uvd_active = false; in amdgpu_dpm_enable_uvd()
1542 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
1544 amdgpu_pm_compute_clocks(adev); in amdgpu_dpm_enable_uvd()
1546 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); in amdgpu_dpm_enable_uvd()
1552 if (adev->asic_type == CHIP_STONEY && in amdgpu_dpm_enable_uvd()
1553 adev->uvd.decode_image_width >= WIDTH_4K) { in amdgpu_dpm_enable_uvd()
1554 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in amdgpu_dpm_enable_uvd()
1565 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_vce() argument
1569 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_vce()
1570 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
1572 adev->pm.dpm.vce_active = true; in amdgpu_dpm_enable_vce()
1574 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; in amdgpu_dpm_enable_vce()
1576 adev->pm.dpm.vce_active = false; in amdgpu_dpm_enable_vce()
1578 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
1580 amdgpu_pm_compute_clocks(adev); in amdgpu_dpm_enable_vce()
1582 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); in amdgpu_dpm_enable_vce()
1589 void amdgpu_pm_print_power_states(struct amdgpu_device *adev) in amdgpu_pm_print_power_states() argument
1593 if (adev->powerplay.pp_funcs->print_power_state == NULL) in amdgpu_pm_print_power_states()
1596 for (i = 0; i < adev->pm.dpm.num_ps; i++) in amdgpu_pm_print_power_states()
1597 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); in amdgpu_pm_print_power_states()
1601 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_jpeg() argument
1605 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); in amdgpu_dpm_enable_jpeg()
1611 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) in amdgpu_pm_load_smu_firmware() argument
1615 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) { in amdgpu_pm_load_smu_firmware()
1616 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle); in amdgpu_pm_load_smu_firmware()
1623 *smu_version = adev->pm.fw_version; in amdgpu_pm_load_smu_firmware()