Lines Matching refs:mclk
3272 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
3275 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
3278 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
3279 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
3282 (pl->mclk + in btc_adjust_clock_combinations()
3286 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
3287 pl->mclk = btc_get_valid_mclk(adev, in btc_adjust_clock_combinations()
3288 max_limits->mclk, in btc_adjust_clock_combinations()
3414 u32 mclk, sclk; in si_apply_state_adjust_rules() local
3475 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3476 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3500 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3501 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3504 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3505 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3508 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3509 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3520 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3523 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3538 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3539 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3544 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3568 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3570 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3571 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3574 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3579 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3580 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3597 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3600 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
4304 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) in si_get_strobe_mode_settings() argument
4310 if (mclk <= pi->mclk_strobe_mode_threshold) in si_get_strobe_mode_settings()
4314 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); in si_get_strobe_mode_settings()
4316 result = si_get_ddr3_mclk_frequency_ratio(mclk); in si_get_strobe_mode_settings()
4572 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, in si_populate_mvdd_value() argument
4579 if (mclk <= pi->mvdd_split_frequency) in si_populate_mvdd_value()
4652 u16 voltage, u32 sclk, u32 mclk, in si_populate_phase_shedding_value() argument
4660 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
4749 pl->mclk); in si_populate_memory_timing_parameters()
4820 table->initialState.level.mclk.vDLL_CNTL = in si_populate_smc_initial_state()
4822 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_initial_state()
4824 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_initial_state()
4826 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_initial_state()
4828 table->initialState.level.mclk.vMPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4830 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_initial_state()
4832 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4834 table->initialState.level.mclk.vMPLL_SS = in si_populate_smc_initial_state()
4836 table->initialState.level.mclk.vMPLL_SS2 = in si_populate_smc_initial_state()
4839 table->initialState.level.mclk.mclk_value = in si_populate_smc_initial_state()
4840 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4890 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4903 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4905 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
5021 table->ACPIState.level.mclk.vDLL_CNTL = in si_populate_smc_acpi_state()
5023 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_acpi_state()
5025 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_acpi_state()
5027 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_acpi_state()
5029 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
5031 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_acpi_state()
5033 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
5035 table->ACPIState.level.mclk.vMPLL_SS = in si_populate_smc_acpi_state()
5037 table->ACPIState.level.mclk.vMPLL_SS2 = in si_populate_smc_acpi_state()
5049 table->ACPIState.level.mclk.mclk_value = 0; in si_populate_smc_acpi_state()
5319 SISLANDS_SMC_MCLK_VALUE *mclk, in si_populate_mclk_value() argument
5391 mclk->mclk_value = cpu_to_be32(memory_clock); in si_populate_mclk_value()
5392 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in si_populate_mclk_value()
5393 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); in si_populate_mclk_value()
5394 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); in si_populate_mclk_value()
5395 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in si_populate_mclk_value()
5396 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in si_populate_mclk_value()
5397 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in si_populate_mclk_value()
5398 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); in si_populate_mclk_value()
5399 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); in si_populate_mclk_value()
5400 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); in si_populate_mclk_value()
5445 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in si_convert_power_level_to_smc()
5456 if (pl->mclk > pi->mclk_edc_enable_threshold) in si_convert_power_level_to_smc()
5459 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
5462 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); in si_convert_power_level_to_smc()
5465 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= in si_convert_power_level_to_smc()
5475 pl->mclk); in si_convert_power_level_to_smc()
5482 pl->mclk, in si_convert_power_level_to_smc()
5483 &level->mclk, in si_convert_power_level_to_smc()
5516 pl->mclk, in si_convert_power_level_to_smc()
5524 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5598 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
6058 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in si_convert_mc_reg_table_entry_to_smc()
7145 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_pplib_clock_info()
7146 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_pplib_clock_info()
7189 pl->mclk = adev->clock.default_mclk; in si_parse_pplib_clock_info()
7199 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
7285 u32 sclk, mclk; in si_parse_power_table() local
7291 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_power_table()
7292 mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_power_table()
7294 adev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
7454 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7494 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7883 return requested_state->performance_levels[0].mclk; in si_dpm_get_mclk()
7885 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; in si_dpm_get_mclk()
7904 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_print_power_state()
7907 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); in si_dpm_print_power_state()
7926 return ((si_cpl1->mclk == si_cpl2->mclk) && in si_are_power_levels_equal()
7984 uint32_t sclk, mclk; in si_dpm_read_sensor() local
8004 mclk = ps->performance_levels[pl_index].mclk; in si_dpm_read_sensor()
8005 *((uint32_t *)value) = mclk; in si_dpm_read_sensor()