720 	u16 pass[32][2][2];  in finetuneDQSI()  local
734 		pass[dqidly][0][0] = 0xff;  in finetuneDQSI()
735 		pass[dqidly][0][1] = 0x0;  in finetuneDQSI()
736 		pass[dqidly][1][0] = 0xff;  in finetuneDQSI()
737 		pass[dqidly][1][1] = 0x0;  in finetuneDQSI()
754 					if (dlli < pass[dqidly][dqsip][0])  in finetuneDQSI()
755 						pass[dqidly][dqsip][0] = (u16) dlli;  in finetuneDQSI()
756 					if (dlli > pass[dqidly][dqsip][1])  in finetuneDQSI()
757 						pass[dqidly][dqsip][1] = (u16) dlli;  in finetuneDQSI()
761 					pass[dqidly][dqsip][0] = 0xff;  in finetuneDQSI()
762 					pass[dqidly][dqsip][1] = 0x0;  in finetuneDQSI()
774 			if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])  in finetuneDQSI()
776 			diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];  in finetuneDQSI()
780 			for (dlli = pass[dqidly][dqsip][0]; dlli > 0  && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);  in finetuneDQSI()
781 			for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);  in finetuneDQSI()
1735 	u32 data, pass, timecnt;  in ddr_phy_init_2500()  local
1737 	pass = 0;  in ddr_phy_init_2500()
1739 	while (!pass) {  in ddr_phy_init_2500()
1748 				pass = 1;  in ddr_phy_init_2500()
1750 		if (!pass) {  in ddr_phy_init_2500()
1895 	u32 data, data2, pass, retrycnt;  in ddr4_init_2500()  local
1930 	pass = 0;  in ddr4_init_2500()
1932 	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {  in ddr4_init_2500()
1934 		pass = 0;  in ddr4_init_2500()
1944 				pass++;  in ddr4_init_2500()
1954 			} else if (pass > 0)  in ddr4_init_2500()
1961 	pass = 0;  in ddr4_init_2500()
1963 	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {  in ddr4_init_2500()
1966 		pass = 0;  in ddr4_init_2500()
1975 				pass++;  in ddr4_init_2500()
1980 			} else if (pass != 0)  in ddr4_init_2500()