23 #define PD_CTRL(n)		(0x0a + ((n) & 0x3)) /* 0..3 */  argument
24 #define RST_CTRL(n)		(0x0e + ((n) & 0x1)) /* 0..1 */  argument
25 #define SYS_CTRL(n)		(0x10 + ((n) & 0x7)) /* 0..4 */  argument
26 #define RGB_DRV(n)		(0x18 + ((n) & 0x3)) /* 0..3 */  argument
27 #define RGB_DLY(n)		(0x1c + ((n) & 0x1)) /* 0..1 */  argument
37 #define HFP_HSW_HBP_HI_HFP(n)		(((n) & 0x300) >> 4)  argument
38 #define HFP_HSW_HBP_HI_HS(n)		(((n) & 0x300) >> 6)  argument
39 #define HFP_HSW_HBP_HI_HBP(n)		(((n) & 0x300) >> 8)  argument
44 #define BIST_POL_BIST_MODE(n)		(((n) & 0xf) << 4)  argument
62 #define OSC_CTRL(n)		(0x48 + ((n) & 0x7)) /* 0..5 */  argument
65 #define PLL_CTRL(n)		(0x50 + ((n) & 0xf)) /* 0..15 */  argument
69 #define PLL_REM(n)		(0x60 + ((n) & 0x3)) /* 0..2 */  argument
70 #define PLL_DIV(n)		(0x63 + ((n) & 0x3)) /* 0..2 */  argument
71 #define PLL_FRAC(n)		(0x66 + ((n) & 0x3)) /* 0..2 */  argument
72 #define PLL_INT(n)		(0x69 + ((n) & 0x1)) /* 0..1 */  argument
74 #define PLL_REF_DIV_P(n)		((n) & 0xf)  argument
76 #define PLL_REF_DIV_S(n)		(((n) & 0x7) << 5)  argument
77 #define PLL_SSC_P(n)		(0x6c + ((n) & 0x3)) /* 0..2 */  argument
78 #define PLL_SSC_STEP(n)		(0x6f + ((n) & 0x3)) /* 0..2 */  argument
79 #define PLL_SSC_OFFSET(n)	(0x72 + ((n) & 0x3)) /* 0..3 */  argument
84 #define GPIO_SEL(n)		(0x7b + ((n) & 0x1)) /* 0..1 */  argument
96 #define DSI_CTRL_DSI_LANES(n)		((n) & 0x3)  argument
99 #define MIPI_PN_SWAP_D(n)		BIT((n) & 0x3)  argument
100 #define MIPI_SOT_SYNC_BIT_(n)	(0x88 + ((n) & 0x1)) /* 0..1 */  argument
115 #define MIPI_PHY_(n)		(0xa0 + ((n) & 0x7)) /* 0..5 */  argument
125 #define MIPI_DBG_SET_(n)	(0xc0 + ((n) & 0xf)) /* 0..9 */  argument
129 #define MIPI_ATE_STATUS_(n)	(0xe3 + ((n) & 0x1)) /* 0..1 */  argument