Lines Matching refs:DISPLAY_VER
238 if (DISPLAY_VER(dev_priv) == 2) in pipe_scanline_is_moving()
278 if (DISPLAY_VER(dev_priv) >= 4) { in intel_wait_for_pipe_off()
805 if (DISPLAY_VER(dev_priv) == 13) in intel_enable_pipe()
864 if (DISPLAY_VER(dev_priv) >= 12) in intel_disable_pipe()
891 if (DISPLAY_VER(dev_priv) == 2) in intel_tile_width_bytes()
906 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv)) in intel_tile_width_bytes()
968 if (DISPLAY_VER(dev_priv) >= 9) in intel_linear_alignment()
973 else if (DISPLAY_VER(dev_priv) >= 4) in intel_linear_alignment()
981 return DISPLAY_VER(i915) >= 5; in has_async_flips()
1001 if (DISPLAY_VER(dev_priv) >= 12) { in intel_surf_alignment()
1040 return DISPLAY_VER(dev_priv) < 4 || in intel_plane_uses_fence()
1200 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) { in intel_pin_and_fence_fb_obj()
1454 if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) || in intel_fb_max_stride()
1457 else if (DISPLAY_VER(dev_priv) >= 7) in intel_fb_max_stride()
1496 if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) && in intel_fb_stride_alignment()
1503 else if (DISPLAY_VER(dev_priv) >= 12) in intel_fb_stride_alignment()
1700 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) in intel_plane_disable_noatomic()
2047 } else if (DISPLAY_VER(dev_priv) >= 13) { in icl_set_pipe_chicken()
2610 if (DISPLAY_VER(dev_priv) == 9) in needs_nv12_wa()
2621 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) in needs_scalerclk_wa()
2821 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) in intel_pre_plane_update()
3245 if (DISPLAY_VER(dev_priv) >= 12) { in icl_pipe_mbus_enable()
3319 if (DISPLAY_VER(dev_priv) >= 13) in icl_ddi_bigjoiner_pre_enable()
3348 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) in hsw_crtc_enable()
3371 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && in hsw_crtc_enable()
3376 if (DISPLAY_VER(dev_priv) >= 9) in hsw_crtc_enable()
3388 if (DISPLAY_VER(dev_priv) < 9) in hsw_crtc_enable()
3393 if (DISPLAY_VER(dev_priv) >= 11) in hsw_crtc_enable()
3399 if (DISPLAY_VER(dev_priv) >= 11) { in hsw_crtc_enable()
3551 else if (DISPLAY_VER(dev_priv) >= 11) in intel_phy_is_combo()
3588 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) in intel_port_to_phy()
3590 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) in intel_port_to_phy()
3607 if (DISPLAY_VER(dev_priv) >= 12) in intel_port_to_tc()
3859 if (DISPLAY_VER(dev_priv) != 2) in i9xx_crtc_enable()
3884 if (DISPLAY_VER(dev_priv) == 2) in i9xx_crtc_enable()
3915 if (DISPLAY_VER(dev_priv) == 2) in i9xx_crtc_disable()
3939 if (DISPLAY_VER(dev_priv) != 2) in i9xx_crtc_disable()
4181 return DISPLAY_VER(dev_priv) < 4 && in intel_crtc_supports_double_wide()
4338 if (DISPLAY_VER(dev_priv) < 4) { in intel_crtc_compute_config()
4384 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && in intel_crtc_compute_config()
4495 return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv); in transcoder_has_m2_n2()
4507 if (DISPLAY_VER(dev_priv) >= 5) { in intel_cpu_transcoder_set_m_n()
4595 if (DISPLAY_VER(dev_priv) > 3) in intel_set_transcoder_timings()
4642 if (DISPLAY_VER(dev_priv) == 2) in intel_pipe_is_interlaced()
4645 if (DISPLAY_VER(dev_priv) >= 9 || in intel_pipe_is_interlaced()
4749 if (DISPLAY_VER(dev_priv) < 4 || in i9xx_set_pipeconf()
4775 return DISPLAY_VER(dev_priv) >= 4 || in i9xx_has_pfit()
4793 if (DISPLAY_VER(dev_priv) < 4) { in i9xx_get_pfit_config()
4961 if (DISPLAY_VER(dev_priv) < 4) in i9xx_get_pipe_config()
4969 if (DISPLAY_VER(dev_priv) >= 4) { in i9xx_get_pipe_config()
5636 if (DISPLAY_VER(dev_priv) > 12) in bdw_set_pipemisc()
5655 if (DISPLAY_VER(dev_priv) >= 11 && in bdw_set_pipemisc()
5660 if (DISPLAY_VER(dev_priv) >= 12) in bdw_set_pipemisc()
5708 if (DISPLAY_VER(dev_priv) > 12) in bdw_get_pipemisc_bpp()
5752 if (DISPLAY_VER(dev_priv) >= 5) { in intel_cpu_transcoder_get_m_n()
5872 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && in ilk_get_pfit_config()
6007 if (DISPLAY_VER(dev_priv) >= 11) in hsw_get_transcoder_state()
6146 if (DISPLAY_VER(dev_priv) >= 12) in hsw_get_ddi_port_state()
6157 if (DISPLAY_VER(dev_priv) < 9 && in hsw_get_ddi_port_state()
6192 if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable) in hsw_get_pipe_config()
6206 DISPLAY_VER(dev_priv) >= 11) { in hsw_get_pipe_config()
6235 if (DISPLAY_VER(dev_priv) >= 9) { in hsw_get_pipe_config()
6257 if (DISPLAY_VER(dev_priv) >= 9) in hsw_get_pipe_config()
6553 else if (DISPLAY_VER(dev_priv) != 2) in i9xx_pll_refclk()
6586 if (DISPLAY_VER(dev_priv) != 2) { in i9xx_crtc_clock_get()
6783 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { in intel_plane_atomic_calc_changes()
6824 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in intel_plane_atomic_calc_changes()
6831 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in intel_plane_atomic_calc_changes()
6838 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) { in intel_plane_atomic_calc_changes()
6955 if (DISPLAY_VER(dev_priv) < 11) in icl_check_nv12_planes()
7116 if (DISPLAY_VER(dev_priv) >= 9) in hsw_compute_linetime_wm()
7143 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && in intel_crtc_atomic_check()
7198 if (DISPLAY_VER(dev_priv) >= 9) { in intel_crtc_atomic_check()
7216 if (DISPLAY_VER(dev_priv) >= 9 || in intel_crtc_atomic_check()
7321 else if (DISPLAY_VER(dev_priv) >= 5) in compute_baseline_pipe_bpp()
7591 if (DISPLAY_VER(dev_priv) >= 9) in intel_dump_pipe_config()
8168 if (DISPLAY_VER(dev_priv) >= 9) in fastboot_enabled()
8390 if (DISPLAY_VER(dev_priv) < 8) { in intel_pipe_config_compare()
8449 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || in intel_pipe_config_compare()
8464 if (DISPLAY_VER(dev_priv) < 4) in intel_pipe_config_compare()
8556 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) in intel_pipe_config_compare()
8648 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) in verify_wm_state()
8661 if (DISPLAY_VER(dev_priv) >= 11 && in verify_wm_state()
9165 if (DISPLAY_VER(dev_priv) == 2) { in intel_crtc_update_active_timings()
10044 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) in intel_crtc_arm_fifo_underrun()
10072 if (DISPLAY_VER(dev_priv) >= 9) { in intel_pipe_fastset()
10090 if (DISPLAY_VER(dev_priv) >= 9 || in intel_pipe_fastset()
10094 if (DISPLAY_VER(dev_priv) >= 11) in intel_pipe_fastset()
10117 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) in commit_pipe_pre_planes()
10142 if (DISPLAY_VER(dev_priv) >= 9 && in commit_pipe_post_planes()
10200 if (DISPLAY_VER(dev_priv) >= 9) in intel_update_crtc()
10678 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) in intel_atomic_commit_tail()
10814 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { in intel_atomic_commit()
10911 if (DISPLAY_VER(to_i915(crtc->dev)) < 6) in add_rps_boost_after_vblank()
11235 if (DISPLAY_VER(dev_priv) >= 9) in intel_ddi_crt_present()
11288 } else if (DISPLAY_VER(dev_priv) >= 12) { in intel_setup_outputs()
11304 } else if (DISPLAY_VER(dev_priv) == 11) { in intel_setup_outputs()
11317 } else if (DISPLAY_VER(dev_priv) >= 9) { in intel_setup_outputs()
11474 } else if (DISPLAY_VER(dev_priv) == 2) { in intel_setup_outputs()
11598 if (DISPLAY_VER(dev_priv) < 4 && in intel_framebuffer_init()
11775 if (DISPLAY_VER(dev_priv) >= 11) { in intel_mode_valid()
11780 } else if (DISPLAY_VER(dev_priv) >= 9 || in intel_mode_valid()
11786 } else if (DISPLAY_VER(dev_priv) >= 3) { in intel_mode_valid()
11810 if (DISPLAY_VER(dev_priv) >= 5) { in intel_mode_valid()
11839 if (DISPLAY_VER(dev_priv) < 9) in intel_mode_valid_max_plane_size()
11847 if (DISPLAY_VER(dev_priv) >= 11) { in intel_mode_valid_max_plane_size()
11890 if (DISPLAY_VER(dev_priv) >= 9) { in intel_init_display_hooks()
11915 if (DISPLAY_VER(dev_priv) >= 9) { in intel_init_display_hooks()
12173 if (DISPLAY_VER(i915) >= 7) { in intel_mode_config_init()
12176 } else if (DISPLAY_VER(i915) >= 4) { in intel_mode_config_init()
12179 } else if (DISPLAY_VER(i915) == 3) { in intel_mode_config_init()
12528 if (DISPLAY_VER(dev_priv) >= 4) in intel_sanitize_plane_mapping()
12587 if (DISPLAY_VER(dev_priv) >= 9 || in intel_sanitize_frame_start_delay()
12659 if (DISPLAY_VER(dev_priv) >= 9) in intel_sanitize_crtc()
12984 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) in intel_modeset_readout_hw_state()
13219 } else if (DISPLAY_VER(dev_priv) >= 9) { in intel_modeset_setup_hw_state()