788 	crtc_state->dpll_hw_state.fp0 = fp;  in i9xx_update_pll_dividers()
792 		crtc_state->dpll_hw_state.fp1 = fp2;  in i9xx_update_pll_dividers()
794 		crtc_state->dpll_hw_state.fp1 = fp;  in i9xx_update_pll_dividers()
862 	crtc_state->dpll_hw_state.dpll = dpll;  in i9xx_compute_dpll()
867 		crtc_state->dpll_hw_state.dpll_md = dpll_md;  in i9xx_compute_dpll()
918 	crtc_state->dpll_hw_state.dpll = dpll;  in i8xx_compute_dpll()
1048 	crtc_state->dpll_hw_state.dpll = dpll;  in ilk_compute_dpll()
1049 	crtc_state->dpll_hw_state.fp0 = fp;  in ilk_compute_dpll()
1050 	crtc_state->dpll_hw_state.fp1 = fp2;  in ilk_compute_dpll()
1062 	memset(&crtc_state->dpll_hw_state, 0,  in ilk_crtc_compute_clock()
1063 	       sizeof(crtc_state->dpll_hw_state));  in ilk_crtc_compute_clock()
1115 	pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |  in vlv_compute_dpll()
1118 		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;  in vlv_compute_dpll()
1122 		pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |  in vlv_compute_dpll()
1125 	pipe_config->dpll_hw_state.dpll_md =  in vlv_compute_dpll()
1132 	pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |  in chv_compute_dpll()
1135 		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;  in chv_compute_dpll()
1139 		pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;  in chv_compute_dpll()
1141 	pipe_config->dpll_hw_state.dpll_md =  in chv_compute_dpll()
1152 	memset(&crtc_state->dpll_hw_state, 0,  in chv_crtc_compute_clock()
1153 	       sizeof(crtc_state->dpll_hw_state));  in chv_crtc_compute_clock()
1174 	memset(&crtc_state->dpll_hw_state, 0,  in vlv_crtc_compute_clock()
1175 	       sizeof(crtc_state->dpll_hw_state));  in vlv_crtc_compute_clock()
1196 	memset(&crtc_state->dpll_hw_state, 0,  in g4x_crtc_compute_clock()
1197 	       sizeof(crtc_state->dpll_hw_state));  in g4x_crtc_compute_clock()
1242 	memset(&crtc_state->dpll_hw_state, 0,  in pnv_crtc_compute_clock()
1243 	       sizeof(crtc_state->dpll_hw_state));  in pnv_crtc_compute_clock()
1279 	memset(&crtc_state->dpll_hw_state, 0,  in i9xx_crtc_compute_clock()
1280 	       sizeof(crtc_state->dpll_hw_state));  in i9xx_crtc_compute_clock()
1316 	memset(&crtc_state->dpll_hw_state, 0,  in i8xx_crtc_compute_clock()
1317 	       sizeof(crtc_state->dpll_hw_state));  in i8xx_crtc_compute_clock()
1381 	u32 dpll = crtc_state->dpll_hw_state.dpll;  in i9xx_enable_pll()
1404 			       crtc_state->dpll_hw_state.dpll_md);  in i9xx_enable_pll()
1457 	intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);  in _vlv_enable_pll()
1476 	if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)  in vlv_enable_pll()
1480 		       pipe_config->dpll_hw_state.dpll_md);  in vlv_enable_pll()
1508 	intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);  in _chv_enable_pll()
1526 	if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)  in chv_enable_pll()
1538 			       pipe_config->dpll_hw_state.dpll_md);  in chv_enable_pll()
1540 		dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;  in chv_enable_pll()
1551 			       pipe_config->dpll_hw_state.dpll_md);  in chv_enable_pll()
1568 		       pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));  in vlv_prepare_pll()
1571 	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)  in vlv_prepare_pll()
1669 		       pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);  in chv_prepare_pll()
1672 	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)  in chv_prepare_pll()