Lines Matching refs:m
22 static int fw_domains_show(struct seq_file *m, void *data) in fw_domains_show() argument
24 struct intel_gt *gt = m->private; in fw_domains_show()
29 seq_printf(m, "user.bypass_count = %u\n", in fw_domains_show()
33 seq_printf(m, "%s.wake_count = %u\n", in fw_domains_show()
41 static void print_rc6_res(struct seq_file *m, in print_rc6_res() argument
45 struct intel_gt *gt = m->private; in print_rc6_res()
49 seq_printf(m, "%s %u (%llu us)\n", title, in print_rc6_res()
54 static int vlv_drpc(struct seq_file *m) in vlv_drpc() argument
56 struct intel_gt *gt = m->private; in vlv_drpc()
63 seq_printf(m, "RC6 Enabled: %s\n", in vlv_drpc()
66 seq_printf(m, "Render Power Well: %s\n", in vlv_drpc()
68 seq_printf(m, "Media Power Well: %s\n", in vlv_drpc()
71 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); in vlv_drpc()
72 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); in vlv_drpc()
74 return fw_domains_show(m, NULL); in vlv_drpc()
77 static int gen6_drpc(struct seq_file *m) in gen6_drpc() argument
79 struct intel_gt *gt = m->private; in gen6_drpc()
99 seq_printf(m, "RC1e Enabled: %s\n", in gen6_drpc()
101 seq_printf(m, "RC6 Enabled: %s\n", in gen6_drpc()
104 seq_printf(m, "Render Well Gating Enabled: %s\n", in gen6_drpc()
106 seq_printf(m, "Media Well Gating Enabled: %s\n", in gen6_drpc()
109 seq_printf(m, "Deep RC6 Enabled: %s\n", in gen6_drpc()
111 seq_printf(m, "Deepest RC6 Enabled: %s\n", in gen6_drpc()
113 seq_puts(m, "Current RC state: "); in gen6_drpc()
117 seq_puts(m, "Core Power Down\n"); in gen6_drpc()
119 seq_puts(m, "on\n"); in gen6_drpc()
122 seq_puts(m, "RC3\n"); in gen6_drpc()
125 seq_puts(m, "RC6\n"); in gen6_drpc()
128 seq_puts(m, "RC7\n"); in gen6_drpc()
131 seq_puts(m, "Unknown\n"); in gen6_drpc()
135 seq_printf(m, "Core Power Down: %s\n", in gen6_drpc()
138 seq_printf(m, "Render Power Well: %s\n", in gen6_drpc()
141 seq_printf(m, "Media Power Well: %s\n", in gen6_drpc()
147 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", in gen6_drpc()
149 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); in gen6_drpc()
150 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); in gen6_drpc()
151 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); in gen6_drpc()
154 seq_printf(m, "RC6 voltage: %dmV\n", in gen6_drpc()
156 seq_printf(m, "RC6+ voltage: %dmV\n", in gen6_drpc()
158 seq_printf(m, "RC6++ voltage: %dmV\n", in gen6_drpc()
162 return fw_domains_show(m, NULL); in gen6_drpc()
165 static int ilk_drpc(struct seq_file *m) in ilk_drpc() argument
167 struct intel_gt *gt = m->private; in ilk_drpc()
176 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); in ilk_drpc()
177 seq_printf(m, "Boost freq: %d\n", in ilk_drpc()
180 seq_printf(m, "HW control enabled: %s\n", in ilk_drpc()
182 seq_printf(m, "SW control enabled: %s\n", in ilk_drpc()
184 seq_printf(m, "Gated voltage change: %s\n", in ilk_drpc()
186 seq_printf(m, "Starting frequency: P%d\n", in ilk_drpc()
188 seq_printf(m, "Max P-state: P%d\n", in ilk_drpc()
190 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); in ilk_drpc()
191 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); in ilk_drpc()
192 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); in ilk_drpc()
193 seq_printf(m, "Render standby enabled: %s\n", in ilk_drpc()
195 seq_puts(m, "Current RS state: "); in ilk_drpc()
198 seq_puts(m, "on\n"); in ilk_drpc()
201 seq_puts(m, "RC1\n"); in ilk_drpc()
204 seq_puts(m, "RC1E\n"); in ilk_drpc()
207 seq_puts(m, "RS1\n"); in ilk_drpc()
210 seq_puts(m, "RS2 (RC6)\n"); in ilk_drpc()
213 seq_puts(m, "RC3 (RC6+)\n"); in ilk_drpc()
216 seq_puts(m, "unknown\n"); in ilk_drpc()
223 static int drpc_show(struct seq_file *m, void *unused) in drpc_show() argument
225 struct intel_gt *gt = m->private; in drpc_show()
232 err = vlv_drpc(m); in drpc_show()
234 err = gen6_drpc(m); in drpc_show()
236 err = ilk_drpc(m); in drpc_show()
243 static int frequency_show(struct seq_file *m, void *unused) in frequency_show() argument
245 struct intel_gt *gt = m->private; in frequency_show()
257 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); in frequency_show()
258 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); in frequency_show()
259 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> in frequency_show()
261 seq_printf(m, "Current P-state: %d\n", in frequency_show()
267 seq_printf(m, "Video Turbo Mode: %s\n", in frequency_show()
269 seq_printf(m, "HW control enabled: %s\n", in frequency_show()
271 seq_printf(m, "SW control enabled: %s\n", in frequency_show()
279 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); in frequency_show()
280 seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq); in frequency_show()
282 seq_printf(m, "actual GPU freq: %d MHz\n", in frequency_show()
285 seq_printf(m, "current GPU freq: %d MHz\n", in frequency_show()
288 seq_printf(m, "max GPU freq: %d MHz\n", in frequency_show()
291 seq_printf(m, "min GPU freq: %d MHz\n", in frequency_show()
294 seq_printf(m, "idle GPU freq: %d MHz\n", in frequency_show()
297 seq_printf(m, "efficient (RPe) frequency: %d MHz\n", in frequency_show()
379 seq_printf(m, "Video Turbo Mode: %s\n", in frequency_show()
381 seq_printf(m, "HW control enabled: %s\n", in frequency_show()
383 seq_printf(m, "SW control enabled: %s\n", in frequency_show()
387 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", in frequency_show()
390 seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", in frequency_show()
392 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", in frequency_show()
394 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); in frequency_show()
395 seq_printf(m, "Render p-state ratio: %d\n", in frequency_show()
397 seq_printf(m, "Render p-state VID: %d\n", in frequency_show()
399 seq_printf(m, "Render p-state limit: %d\n", in frequency_show()
401 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); in frequency_show()
402 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); in frequency_show()
403 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); in frequency_show()
404 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); in frequency_show()
405 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); in frequency_show()
406 seq_printf(m, "CAGF: %dMHz\n", cagf); in frequency_show()
407 seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", in frequency_show()
410 seq_printf(m, "RP CUR UP: %d (%lldns)\n", in frequency_show()
412 seq_printf(m, "RP PREV UP: %d (%lldns)\n", in frequency_show()
414 seq_printf(m, "Up threshold: %d%%\n", in frequency_show()
416 seq_printf(m, "RP UP EI: %d (%lldns)\n", in frequency_show()
418 seq_printf(m, "RP UP THRESHOLD: %d (%lldns)\n", in frequency_show()
421 seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", in frequency_show()
424 seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", in frequency_show()
427 seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", in frequency_show()
430 seq_printf(m, "Down threshold: %d%%\n", in frequency_show()
432 seq_printf(m, "RP DOWN EI: %d (%lldns)\n", in frequency_show()
434 seq_printf(m, "RP DOWN THRESHOLD: %d (%lldns)\n", in frequency_show()
441 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", in frequency_show()
447 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", in frequency_show()
454 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", in frequency_show()
456 seq_printf(m, "Max overclocked frequency: %dMHz\n", in frequency_show()
459 seq_printf(m, "Current freq: %d MHz\n", in frequency_show()
461 seq_printf(m, "Actual freq: %d MHz\n", cagf); in frequency_show()
462 seq_printf(m, "Idle freq: %d MHz\n", in frequency_show()
464 seq_printf(m, "Min freq: %d MHz\n", in frequency_show()
466 seq_printf(m, "Boost freq: %d MHz\n", in frequency_show()
468 seq_printf(m, "Max freq: %d MHz\n", in frequency_show()
470 seq_printf(m, in frequency_show()
474 seq_puts(m, "no P-state info available\n"); in frequency_show()
477 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); in frequency_show()
478 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq); in frequency_show()
479 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); in frequency_show()
487 static int llc_show(struct seq_file *m, void *data) in llc_show() argument
489 struct intel_gt *gt = m->private; in llc_show()
497 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(i915))); in llc_show()
498 seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC", in llc_show()
509 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); in llc_show()
517 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", in llc_show()
554 static int rps_boost_show(struct seq_file *m, void *data) in rps_boost_show() argument
556 struct intel_gt *gt = m->private; in rps_boost_show()
560 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps))); in rps_boost_show()
561 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps))); in rps_boost_show()
562 seq_printf(m, "GPU busy? %s, %llums\n", in rps_boost_show()
565 seq_printf(m, "Boosts outstanding? %d\n", in rps_boost_show()
567 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); in rps_boost_show()
568 seq_printf(m, "Frequency requested %d, actual %d\n", in rps_boost_show()
571 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", in rps_boost_show()
576 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", in rps_boost_show()
581 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); in rps_boost_show()
595 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", in rps_boost_show()
597 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", in rps_boost_show()
600 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", in rps_boost_show()
604 seq_puts(m, "\nRPS Autotuning inactive\n"); in rps_boost_show()