3911 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
3933 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
3956 			&crtc_state->wm.skl.optimal.planes[plane_id];  in tgl_crtc_can_enable_sagv()
4035 		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;  in intel_compute_sagv_mask()
4226 	crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;  in skl_crtc_allocate_ddb()
4227 	crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;  in skl_crtc_allocate_ddb()
5140 	memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));  in skl_allocate_plane_ddb()
5141 	memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));  in skl_allocate_plane_ddb()
5160 	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =  in skl_allocate_plane_ddb()
5162 	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;  in skl_allocate_plane_ddb()
5175 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_allocate_plane_ddb()
5212 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_allocate_plane_ddb()
5251 			&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_allocate_plane_ddb()
5253 			&crtc_state->wm.skl.plane_ddb_uv[plane_id];  in skl_allocate_plane_ddb()
5285 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_allocate_plane_ddb()
5309 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_allocate_plane_ddb()
5753 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];  in skl_build_plane_wm_single()
5781 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];  in skl_build_plane_wm_uv()
5803 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];  in skl_build_plane_wm()
5833 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];  in icl_build_plane_wm()
5897 	crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;  in skl_build_pipe_wm()
5936 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;  in skl_write_plane_wm()
5939 		&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_write_plane_wm()
5941 		&crtc_state->wm.skl.plane_ddb_uv[plane_id];  in skl_write_plane_wm()
5979 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;  in skl_write_cursor_wm()
5981 		&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_write_cursor_wm()
6078 		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],  in skl_ddb_add_affected_planes()
6079 					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&  in skl_ddb_add_affected_planes()
6080 		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],  in skl_ddb_add_affected_planes()
6081 					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))  in skl_ddb_add_affected_planes()
6243 		old_pipe_wm = &old_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
6244 		new_pipe_wm = &new_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
6250 			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_print_wm_changes()
6251 			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_print_wm_changes()
6437 						 &old_crtc_state->wm.skl.optimal,  in skl_wm_add_affected_planes()
6438 						 &new_crtc_state->wm.skl.optimal))  in skl_wm_add_affected_planes()
6647 		memset(&crtc_state->wm.skl.optimal, 0,  in skl_wm_get_hw_state()
6648 		       sizeof(crtc_state->wm.skl.optimal));  in skl_wm_get_hw_state()
6650 			skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);  in skl_wm_get_hw_state()
6651 		crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;  in skl_wm_get_hw_state()
6657 				&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_wm_get_hw_state()
6659 				&crtc_state->wm.skl.plane_ddb_uv[plane_id];  in skl_wm_get_hw_state()
6680 		crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;  in skl_wm_get_hw_state()
6681 		crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;  in skl_wm_get_hw_state()
6685 			skl_ddb_dbuf_slice_mask(dev_priv, &crtc_state->wm.skl.ddb);  in skl_wm_get_hw_state()
6709 		entries[crtc->pipe] = crtc_state->wm.skl.ddb;  in skl_dbuf_is_misconfigured()
6722 		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries,  in skl_dbuf_is_misconfigured()
6762 		memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));  in skl_wm_sanitize()