200 	u32 cr;  in mcde_configure_extsrc()  local
205 		cr = MCDE_EXTSRC0CR;  in mcde_configure_extsrc()
209 		cr = MCDE_EXTSRC1CR;  in mcde_configure_extsrc()
213 		cr = MCDE_EXTSRC2CR;  in mcde_configure_extsrc()
217 		cr = MCDE_EXTSRC3CR;  in mcde_configure_extsrc()
221 		cr = MCDE_EXTSRC4CR;  in mcde_configure_extsrc()
225 		cr = MCDE_EXTSRC5CR;  in mcde_configure_extsrc()
229 		cr = MCDE_EXTSRC6CR;  in mcde_configure_extsrc()
233 		cr = MCDE_EXTSRC7CR;  in mcde_configure_extsrc()
237 		cr = MCDE_EXTSRC8CR;  in mcde_configure_extsrc()
241 		cr = MCDE_EXTSRC9CR;  in mcde_configure_extsrc()
332 	writel(val, mcde->regs + cr);  in mcde_configure_extsrc()
348 	u32 cr;  in mcde_configure_overlay()  local
358 		cr = MCDE_OVL0CR;  in mcde_configure_overlay()
366 		cr = MCDE_OVL1CR;  in mcde_configure_overlay()
374 		cr = MCDE_OVL2CR;  in mcde_configure_overlay()
382 		cr = MCDE_OVL3CR;  in mcde_configure_overlay()
390 		cr = MCDE_OVL4CR;  in mcde_configure_overlay()
398 		cr = MCDE_OVL5CR;  in mcde_configure_overlay()
479 	writel(val, mcde->regs + cr);  in mcde_configure_overlay()
846 	u32 cr;  in mcde_enable_fifo()  local
850 		cr = MCDE_CRA0;  in mcde_enable_fifo()
853 		cr = MCDE_CRB0;  in mcde_enable_fifo()
862 	val = readl(mcde->regs + cr);  in mcde_enable_fifo()
864 	writel(val, mcde->regs + cr);  in mcde_enable_fifo()
874 	u32 cr;  in mcde_disable_fifo()  local
878 		cr = MCDE_CRA0;  in mcde_disable_fifo()
881 		cr = MCDE_CRB0;  in mcde_disable_fifo()
890 	val = readl(mcde->regs + cr);  in mcde_disable_fifo()
892 	writel(val, mcde->regs + cr);  in mcde_disable_fifo()
900 	while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) {  in mcde_disable_fifo()