39 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);  in a6xx_gmu_irq()
63 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);  in a6xx_hfi_irq()
142 	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);  in a6xx_gmu_set_freq()
144 	gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,  in a6xx_gmu_set_freq()
151 	gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);  in a6xx_gmu_set_freq()
215 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);  in a6xx_gmu_start()
220 	gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);  in a6xx_gmu_start()
222 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);  in a6xx_gmu_start()
238 	gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);  in a6xx_gmu_hfi_start()
319 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);  in a6xx_gmu_set_oob()
332 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);  in a6xx_gmu_set_oob()
352 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);  in a6xx_gmu_clear_oob()
364 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);  in a6xx_sptprac_enable()
389 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);  in a6xx_sptprac_disable()
405 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);  in a6xx_gmu_gfx_rail_on()
410 	gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);  in a6xx_gmu_gfx_rail_on()
411 	gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);  in a6xx_gmu_gfx_rail_on()
423 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);  in a6xx_gmu_notify_slumber()
435 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);  in a6xx_gmu_notify_slumber()
451 	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);  in a6xx_gmu_notify_slumber()
460 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);  in a6xx_rpmh_start()
479 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_start()
482 	gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);  in a6xx_rpmh_start()
486 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);  in a6xx_rpmh_start()
495 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);  in a6xx_rpmh_stop()
502 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_stop()
639 	gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);  in a6xx_gmu_power_config()
640 	gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
641 	gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
643 	gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);  in a6xx_gmu_power_config()
647 		gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,  in a6xx_gmu_power_config()
654 		gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,  in a6xx_gmu_power_config()
759 		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);  in a6xx_gmu_fw_start()
760 		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);  in a6xx_gmu_fw_start()
773 		gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);  in a6xx_gmu_fw_start()
790 	gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);  in a6xx_gmu_fw_start()
791 	gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);  in a6xx_gmu_fw_start()
794 	gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);  in a6xx_gmu_fw_start()
795 	gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);  in a6xx_gmu_fw_start()
797 	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,  in a6xx_gmu_fw_start()
805 	gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);  in a6xx_gmu_fw_start()
807 	gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,  in a6xx_gmu_fw_start()
853 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);  in a6xx_gmu_irq_disable()
854 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);  in a6xx_gmu_irq_disable()
952 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);  in a6xx_gmu_resume()
953 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);  in a6xx_gmu_resume()
979 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);  in a6xx_gmu_resume()
980 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);  in a6xx_gmu_resume()