129 static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,  in dpu_hw_intr_clear_intr_status_nolock()  argument
134 	if (!intr)  in dpu_hw_intr_clear_intr_status_nolock()
138 	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx));  in dpu_hw_intr_clear_intr_status_nolock()
144 static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,  in dpu_hw_intr_dispatch_irq()  argument
155 	if (!intr)  in dpu_hw_intr_dispatch_irq()
163 	spin_lock_irqsave(&intr->irq_lock, irq_flags);  in dpu_hw_intr_dispatch_irq()
165 		if (!test_bit(reg_idx, &intr->irq_mask))  in dpu_hw_intr_dispatch_irq()
169 		irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);  in dpu_hw_intr_dispatch_irq()
172 		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);  in dpu_hw_intr_dispatch_irq()
176 			DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,  in dpu_hw_intr_dispatch_irq()
200 			dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);  in dpu_hw_intr_dispatch_irq()
214 	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);  in dpu_hw_intr_dispatch_irq()
217 static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)  in dpu_hw_intr_enable_irq_locked()  argument
224 	if (!intr)  in dpu_hw_intr_enable_irq_locked()
227 	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {  in dpu_hw_intr_enable_irq_locked()
237 	assert_spin_locked(&intr->irq_lock);  in dpu_hw_intr_enable_irq_locked()
242 	cache_irq_mask = intr->cache_irq_mask[reg_idx];  in dpu_hw_intr_enable_irq_locked()
250 		DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));  in dpu_hw_intr_enable_irq_locked()
252 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);  in dpu_hw_intr_enable_irq_locked()
257 		intr->cache_irq_mask[reg_idx] = cache_irq_mask;  in dpu_hw_intr_enable_irq_locked()
266 static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)  in dpu_hw_intr_disable_irq_locked()  argument
273 	if (!intr)  in dpu_hw_intr_disable_irq_locked()
276 	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {  in dpu_hw_intr_disable_irq_locked()
286 	assert_spin_locked(&intr->irq_lock);  in dpu_hw_intr_disable_irq_locked()
291 	cache_irq_mask = intr->cache_irq_mask[reg_idx];  in dpu_hw_intr_disable_irq_locked()
299 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);  in dpu_hw_intr_disable_irq_locked()
301 		DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));  in dpu_hw_intr_disable_irq_locked()
306 		intr->cache_irq_mask[reg_idx] = cache_irq_mask;  in dpu_hw_intr_disable_irq_locked()
315 static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr)  in dpu_hw_intr_clear_irqs()  argument
319 	if (!intr)  in dpu_hw_intr_clear_irqs()
323 		if (test_bit(i, &intr->irq_mask))  in dpu_hw_intr_clear_irqs()
324 			DPU_REG_WRITE(&intr->hw,  in dpu_hw_intr_clear_irqs()
334 static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr)  in dpu_hw_intr_disable_irqs()  argument
338 	if (!intr)  in dpu_hw_intr_disable_irqs()
342 		if (test_bit(i, &intr->irq_mask))  in dpu_hw_intr_disable_irqs()
343 			DPU_REG_WRITE(&intr->hw,  in dpu_hw_intr_disable_irqs()
353 static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,  in dpu_hw_intr_get_interrupt_status()  argument
360 	if (!intr)  in dpu_hw_intr_get_interrupt_status()
363 	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {  in dpu_hw_intr_get_interrupt_status()
368 	spin_lock_irqsave(&intr->irq_lock, irq_flags);  in dpu_hw_intr_get_interrupt_status()
371 	intr_status = DPU_REG_READ(&intr->hw,  in dpu_hw_intr_get_interrupt_status()
375 		DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,  in dpu_hw_intr_get_interrupt_status()
381 	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);  in dpu_hw_intr_get_interrupt_status()
386 static unsigned long dpu_hw_intr_lock(struct dpu_hw_intr *intr)  in dpu_hw_intr_lock()  argument
390 	spin_lock_irqsave(&intr->irq_lock, irq_flags);  in dpu_hw_intr_lock()
395 static void dpu_hw_intr_unlock(struct dpu_hw_intr *intr, unsigned long irq_flags)  in dpu_hw_intr_unlock()  argument
397 	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);  in dpu_hw_intr_unlock()
423 	struct dpu_hw_intr *intr;  in dpu_hw_intr_init()  local
428 	intr = kzalloc(sizeof(*intr), GFP_KERNEL);  in dpu_hw_intr_init()
429 	if (!intr)  in dpu_hw_intr_init()
432 	__intr_offset(m, addr, &intr->hw);  in dpu_hw_intr_init()
433 	__setup_intr_ops(&intr->ops);  in dpu_hw_intr_init()
435 	intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32;  in dpu_hw_intr_init()
437 	intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),  in dpu_hw_intr_init()
439 	if (intr->cache_irq_mask == NULL) {  in dpu_hw_intr_init()
440 		kfree(intr);  in dpu_hw_intr_init()
444 	intr->irq_mask = m->mdss_irqs;  in dpu_hw_intr_init()
446 	spin_lock_init(&intr->irq_lock);  in dpu_hw_intr_init()
448 	return intr;  in dpu_hw_intr_init()
451 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr)  in dpu_hw_intr_destroy()  argument
453 	if (intr) {  in dpu_hw_intr_destroy()
454 		kfree(intr->cache_irq_mask);  in dpu_hw_intr_destroy()
455 		kfree(intr);  in dpu_hw_intr_destroy()