Lines Matching refs:idx
138 u32 *idx) in _sspp_subblk_offset() argument
150 *idx = sblk->src_blk.base; in _sspp_subblk_offset()
155 *idx = sblk->scaler_blk.base; in _sspp_subblk_offset()
159 *idx = sblk->csc_blk.base; in _sspp_subblk_offset()
173 u32 idx; in dpu_hw_sspp_setup_multirect() local
175 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) in dpu_hw_sspp_setup_multirect()
186 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); in dpu_hw_sspp_setup_multirect()
194 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); in dpu_hw_sspp_setup_multirect()
200 u32 idx; in _sspp_setup_opmode() local
204 _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || in _sspp_setup_opmode()
208 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); in _sspp_setup_opmode()
215 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); in _sspp_setup_opmode()
221 u32 idx; in _sspp_setup_csc10_opmode() local
224 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC_10BIT, &idx)) in _sspp_setup_csc10_opmode()
227 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); in _sspp_setup_csc10_opmode()
233 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); in _sspp_setup_csc10_opmode()
248 u32 idx; in dpu_hw_sspp_setup_format() local
250 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt) in dpu_hw_sspp_setup_format()
264 opmode = DPU_REG_READ(c, op_mode_off + idx); in dpu_hw_sspp_setup_format()
348 DPU_REG_WRITE(c, format_off + idx, src_format); in dpu_hw_sspp_setup_format()
349 DPU_REG_WRITE(c, unpack_pat_off + idx, unpack); in dpu_hw_sspp_setup_format()
350 DPU_REG_WRITE(c, op_mode_off + idx, opmode); in dpu_hw_sspp_setup_format()
353 DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); in dpu_hw_sspp_setup_format()
364 u32 idx; in dpu_hw_sspp_setup_pe_config() local
366 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !pe_ext) in dpu_hw_sspp_setup_pe_config()
396 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]); in dpu_hw_sspp_setup_pe_config()
397 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]); in dpu_hw_sspp_setup_pe_config()
398 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx, in dpu_hw_sspp_setup_pe_config()
402 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]); in dpu_hw_sspp_setup_pe_config()
403 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]); in dpu_hw_sspp_setup_pe_config()
404 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx, in dpu_hw_sspp_setup_pe_config()
408 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]); in dpu_hw_sspp_setup_pe_config()
409 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]); in dpu_hw_sspp_setup_pe_config()
410 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx, in dpu_hw_sspp_setup_pe_config()
419 u32 idx; in _dpu_hw_sspp_setup_scaler3() local
423 if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp in _dpu_hw_sspp_setup_scaler3()
427 dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, in _dpu_hw_sspp_setup_scaler3()
434 u32 idx; in _dpu_hw_sspp_get_scaler3_ver() local
436 if (!ctx || _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)) in _dpu_hw_sspp_get_scaler3_ver()
439 return dpu_hw_get_scaler3_ver(&ctx->hw, idx); in _dpu_hw_sspp_get_scaler3_ver()
452 u32 idx; in dpu_hw_sspp_setup_rects() local
454 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg) in dpu_hw_sspp_setup_rects()
486 ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); in dpu_hw_sspp_setup_rects()
487 ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); in dpu_hw_sspp_setup_rects()
505 DPU_REG_WRITE(c, src_size_off + idx, src_size); in dpu_hw_sspp_setup_rects()
506 DPU_REG_WRITE(c, src_xy_off + idx, src_xy); in dpu_hw_sspp_setup_rects()
507 DPU_REG_WRITE(c, out_size_off + idx, dst_size); in dpu_hw_sspp_setup_rects()
508 DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); in dpu_hw_sspp_setup_rects()
510 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); in dpu_hw_sspp_setup_rects()
511 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); in dpu_hw_sspp_setup_rects()
519 u32 idx; in dpu_hw_sspp_setup_sourceaddress() local
521 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) in dpu_hw_sspp_setup_sourceaddress()
526 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, in dpu_hw_sspp_setup_sourceaddress()
529 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, in dpu_hw_sspp_setup_sourceaddress()
531 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, in dpu_hw_sspp_setup_sourceaddress()
534 DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, in dpu_hw_sspp_setup_sourceaddress()
536 DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, in dpu_hw_sspp_setup_sourceaddress()
544 u32 idx; in dpu_hw_sspp_setup_csc() local
547 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC, &idx) || !data) in dpu_hw_sspp_setup_csc()
551 idx += CSC_10BIT_OFFSET; in dpu_hw_sspp_setup_csc()
555 dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); in dpu_hw_sspp_setup_csc()
561 u32 idx; in dpu_hw_sspp_setup_solidfill() local
563 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) in dpu_hw_sspp_setup_solidfill()
567 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); in dpu_hw_sspp_setup_solidfill()
569 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, in dpu_hw_sspp_setup_solidfill()
576 u32 idx; in dpu_hw_sspp_setup_danger_safe_lut() local
578 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) in dpu_hw_sspp_setup_danger_safe_lut()
581 DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut); in dpu_hw_sspp_setup_danger_safe_lut()
582 DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut); in dpu_hw_sspp_setup_danger_safe_lut()
588 u32 idx; in dpu_hw_sspp_setup_creq_lut() local
590 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) in dpu_hw_sspp_setup_creq_lut()
594 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut); in dpu_hw_sspp_setup_creq_lut()
595 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx, in dpu_hw_sspp_setup_creq_lut()
598 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut); in dpu_hw_sspp_setup_creq_lut()
605 u32 idx; in dpu_hw_sspp_setup_qos_ctrl() local
608 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) in dpu_hw_sspp_setup_qos_ctrl()
624 DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); in dpu_hw_sspp_setup_qos_ctrl()
630 u32 idx; in dpu_hw_sspp_setup_cdp() local
636 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) in dpu_hw_sspp_setup_cdp()
711 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, in dpu_hw_sspp_init() argument
725 cfg = _sspp_offset(idx, addr, catalog, &hw_pipe->hw); in dpu_hw_sspp_init()
734 hw_pipe->idx = idx; in dpu_hw_sspp_init()