57 enum mdp4_pipe {  enum
598 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE()
600 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_SIZE()
614 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_XY()
628 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }  in REG_MDP4_PIPE_DST_SIZE()
642 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }  in REG_MDP4_PIPE_DST_XY()
656 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP0_BASE()
658 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP1_BASE()
660 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP2_BASE()
662 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0…  in REG_MDP4_PIPE_SRCP3_BASE()
664 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_A()
678 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_B()
692 static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x1…  in REG_MDP4_PIPE_SSTILE_FRAME_SIZE()
706 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_FORMAT()
767 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_UNPACK()
793 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }  in REG_MDP4_PIPE_OP_MODE()
818 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i…  in REG_MDP4_PIPE_PHASEX_STEP()
820 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i…  in REG_MDP4_PIPE_PHASEY_STEP()
822 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*…  in REG_MDP4_PIPE_FETCH_CONFIG()
824 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i…  in REG_MDP4_PIPE_SOLID_COLOR()
826 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }  in REG_MDP4_PIPE_CSC()
829 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0…  in REG_MDP4_PIPE_CSC_MV()
831 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400…  in REG_MDP4_PIPE_CSC_MV_VAL()
833 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500…  in REG_MDP4_PIPE_CSC_PRE_BV()
835 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x0002…  in REG_MDP4_PIPE_CSC_PRE_BV_VAL()
837 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x0002458…  in REG_MDP4_PIPE_CSC_POST_BV()
839 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP4_PIPE_CSC_POST_BV_VAL()
841 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600…  in REG_MDP4_PIPE_CSC_PRE_LV()
843 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x0002…  in REG_MDP4_PIPE_CSC_PRE_LV_VAL()
845 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x0002468…  in REG_MDP4_PIPE_CSC_POST_LV()
847 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP4_PIPE_CSC_POST_LV_VAL()