29 		mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);  in mdp4_hw_init()
30 		mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);  in mdp4_hw_init()
33 	mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);  in mdp4_hw_init()
36 	mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);  in mdp4_hw_init()
50 	mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);  in mdp4_hw_init()
51 	mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);  in mdp4_hw_init()
53 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);  in mdp4_hw_init()
54 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);  in mdp4_hw_init()
55 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);  in mdp4_hw_init()
56 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);  in mdp4_hw_init()
59 		mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);  in mdp4_hw_init()
60 	mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);  in mdp4_hw_init()
63 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);  in mdp4_hw_init()
64 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);  in mdp4_hw_init()
65 	mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);  in mdp4_hw_init()
66 	mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);  in mdp4_hw_init()
67 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);  in mdp4_hw_init()
68 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);  in mdp4_hw_init()
71 		mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);  in mdp4_hw_init()
509 	mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);  in mdp4_kms_init()
510 	mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);  in mdp4_kms_init()
511 	mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);  in mdp4_kms_init()