Lines Matching refs:pll
81 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) in pll_get_phy() argument
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
97 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, in hdmi_tx_chan_write() argument
100 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
398 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); in hdmi_8996_pll_set_clk_rate() local
399 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_8996_pll_set_clk_rate()
417 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x04); in hdmi_8996_pll_set_clk_rate()
420 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL, 0x20); in hdmi_8996_pll_set_clk_rate()
425 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
428 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
431 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
436 hdmi_tx_chan_write(pll, 0, REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE, in hdmi_8996_pll_set_clk_rate()
438 hdmi_tx_chan_write(pll, 2, REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE, in hdmi_8996_pll_set_clk_rate()
441 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1E); in hdmi_8996_pll_set_clk_rate()
442 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x07); in hdmi_8996_pll_set_clk_rate()
443 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL, 0x37); in hdmi_8996_pll_set_clk_rate()
444 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL, 0x02); in hdmi_8996_pll_set_clk_rate()
445 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1, 0x0E); in hdmi_8996_pll_set_clk_rate()
448 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL, in hdmi_8996_pll_set_clk_rate()
451 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_TRIM, 0x0F); in hdmi_8996_pll_set_clk_rate()
452 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_IVCO, 0x0F); in hdmi_8996_pll_set_clk_rate()
453 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL, in hdmi_8996_pll_set_clk_rate()
456 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x06); in hdmi_8996_pll_set_clk_rate()
458 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_SELECT, 0x30); in hdmi_8996_pll_set_clk_rate()
459 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL, in hdmi_8996_pll_set_clk_rate()
461 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN, in hdmi_8996_pll_set_clk_rate()
464 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0, in hdmi_8996_pll_set_clk_rate()
466 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0, in hdmi_8996_pll_set_clk_rate()
468 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0, in hdmi_8996_pll_set_clk_rate()
470 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0, in hdmi_8996_pll_set_clk_rate()
472 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0, in hdmi_8996_pll_set_clk_rate()
474 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0, in hdmi_8996_pll_set_clk_rate()
476 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0, in hdmi_8996_pll_set_clk_rate()
479 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0, in hdmi_8996_pll_set_clk_rate()
481 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0, in hdmi_8996_pll_set_clk_rate()
484 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0, in hdmi_8996_pll_set_clk_rate()
486 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0, in hdmi_8996_pll_set_clk_rate()
488 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0, in hdmi_8996_pll_set_clk_rate()
491 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP, 0x00); in hdmi_8996_pll_set_clk_rate()
492 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN, in hdmi_8996_pll_set_clk_rate()
494 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV, in hdmi_8996_pll_set_clk_rate()
496 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG, 0x02); in hdmi_8996_pll_set_clk_rate()
498 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM, 0x15); in hdmi_8996_pll_set_clk_rate()
502 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
505 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
508 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
511 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
514 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
517 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
520 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
523 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
526 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_set_clk_rate()
567 static int hdmi_8996_pll_lock_status(struct hdmi_pll_8996 *pll) in hdmi_8996_pll_lock_status() argument
577 status = hdmi_pll_read(pll, in hdmi_8996_pll_lock_status()
594 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); in hdmi_8996_pll_prepare() local
595 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_8996_pll_prepare()
604 ret = hdmi_8996_pll_lock_status(pll); in hdmi_8996_pll_prepare()
609 hdmi_tx_chan_write(pll, i, in hdmi_8996_pll_prepare()
614 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER1, 0x0); in hdmi_8996_pll_prepare()
615 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER2, 0x0); in hdmi_8996_pll_prepare()
616 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1, 0x0); in hdmi_8996_pll_prepare()
617 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2, 0x0); in hdmi_8996_pll_prepare()
618 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER, 0x2); in hdmi_8996_pll_prepare()
647 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); in hdmi_8996_pll_recalc_rate() local
651 cmp1 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0); in hdmi_8996_pll_recalc_rate()
652 cmp2 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0); in hdmi_8996_pll_recalc_rate()
653 cmp3 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0); in hdmi_8996_pll_recalc_rate()
666 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); in hdmi_8996_pll_unprepare() local
667 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_8996_pll_unprepare()
675 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); in hdmi_8996_pll_is_enabled() local
679 status = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS); in hdmi_8996_pll_is_enabled()
709 struct hdmi_pll_8996 *pll; in msm_hdmi_pll_8996_init() local
713 pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); in msm_hdmi_pll_8996_init()
714 if (!pll) in msm_hdmi_pll_8996_init()
717 pll->pdev = pdev; in msm_hdmi_pll_8996_init()
719 pll->mmio_qserdes_com = msm_ioremap(pdev, "hdmi_pll", "HDMI_PLL"); in msm_hdmi_pll_8996_init()
720 if (IS_ERR(pll->mmio_qserdes_com)) { in msm_hdmi_pll_8996_init()
731 pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name, label); in msm_hdmi_pll_8996_init()
732 if (IS_ERR(pll->mmio_qserdes_tx[i])) { in msm_hdmi_pll_8996_init()
737 pll->clk_hw.init = &pll_init; in msm_hdmi_pll_8996_init()
739 clk = devm_clk_register(dev, &pll->clk_hw); in msm_hdmi_pll_8996_init()