Lines Matching refs:rdev
44 void r420_pm_init_profile(struct radeon_device *rdev) in r420_pm_init_profile() argument
47 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
48 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
49 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
50 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
52 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
53 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in r420_pm_init_profile()
54 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
55 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
57 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
58 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r420_pm_init_profile()
59 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
60 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
62 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
63 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
64 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
65 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
67 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
68 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
69 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
70 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
72 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
73 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
74 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
75 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
77 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
78 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
79 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
80 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
83 static void r420_set_reg_safe(struct radeon_device *rdev) in r420_set_reg_safe() argument
85 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; in r420_set_reg_safe()
86 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); in r420_set_reg_safe()
89 void r420_pipes_init(struct radeon_device *rdev) in r420_pipes_init() argument
99 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
107 if ((rdev->pdev->device == 0x5e4c) || in r420_pipes_init()
108 (rdev->pdev->device == 0x5e4f)) in r420_pipes_init()
111 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
135 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
147 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
151 if (rdev->family == CHIP_RV530) { in r420_pipes_init()
154 rdev->num_z_pipes = 2; in r420_pipes_init()
156 rdev->num_z_pipes = 1; in r420_pipes_init()
158 rdev->num_z_pipes = 1; in r420_pipes_init()
161 rdev->num_gb_pipes, rdev->num_z_pipes); in r420_pipes_init()
164 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) in r420_mc_rreg() argument
169 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
172 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
176 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r420_mc_wreg() argument
180 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
184 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
187 static void r420_debugfs(struct radeon_device *rdev) in r420_debugfs() argument
189 r100_debugfs_rbbm_init(rdev); in r420_debugfs()
190 r420_debugfs_pipes_info_init(rdev); in r420_debugfs()
193 static void r420_clock_resume(struct radeon_device *rdev) in r420_clock_resume() argument
198 radeon_atom_set_clock_gating(rdev, 1); in r420_clock_resume()
201 if (rdev->family == CHIP_R420) in r420_clock_resume()
206 static void r420_cp_errata_init(struct radeon_device *rdev) in r420_cp_errata_init() argument
209 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_init()
217 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); in r420_cp_errata_init()
218 r = radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_init()
221 radeon_ring_write(ring, rdev->config.r300.resync_scratch); in r420_cp_errata_init()
223 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_init()
226 static void r420_cp_errata_fini(struct radeon_device *rdev) in r420_cp_errata_fini() argument
229 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_fini()
234 r = radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_fini()
238 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_fini()
239 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); in r420_cp_errata_fini()
242 static int r420_startup(struct radeon_device *rdev) in r420_startup() argument
247 r100_set_common_regs(rdev); in r420_startup()
249 r300_mc_program(rdev); in r420_startup()
251 r420_clock_resume(rdev); in r420_startup()
254 if (rdev->flags & RADEON_IS_PCIE) { in r420_startup()
255 r = rv370_pcie_gart_enable(rdev); in r420_startup()
259 if (rdev->flags & RADEON_IS_PCI) { in r420_startup()
260 r = r100_pci_gart_enable(rdev); in r420_startup()
264 r420_pipes_init(rdev); in r420_startup()
267 r = radeon_wb_init(rdev); in r420_startup()
271 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r420_startup()
273 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r420_startup()
278 if (!rdev->irq.installed) { in r420_startup()
279 r = radeon_irq_kms_init(rdev); in r420_startup()
284 r100_irq_set(rdev); in r420_startup()
285 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r420_startup()
287 r = r100_cp_init(rdev, 1024 * 1024); in r420_startup()
289 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r420_startup()
292 r420_cp_errata_init(rdev); in r420_startup()
294 r = radeon_ib_pool_init(rdev); in r420_startup()
296 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r420_startup()
303 int r420_resume(struct radeon_device *rdev) in r420_resume() argument
308 if (rdev->flags & RADEON_IS_PCIE) in r420_resume()
309 rv370_pcie_gart_disable(rdev); in r420_resume()
310 if (rdev->flags & RADEON_IS_PCI) in r420_resume()
311 r100_pci_gart_disable(rdev); in r420_resume()
313 r420_clock_resume(rdev); in r420_resume()
315 if (radeon_asic_reset(rdev)) { in r420_resume()
316 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r420_resume()
321 if (rdev->is_atom_bios) { in r420_resume()
322 atom_asic_init(rdev->mode_info.atom_context); in r420_resume()
324 radeon_combios_asic_init(rdev->ddev); in r420_resume()
327 r420_clock_resume(rdev); in r420_resume()
329 radeon_surface_init(rdev); in r420_resume()
331 rdev->accel_working = true; in r420_resume()
332 r = r420_startup(rdev); in r420_resume()
334 rdev->accel_working = false; in r420_resume()
339 int r420_suspend(struct radeon_device *rdev) in r420_suspend() argument
341 radeon_pm_suspend(rdev); in r420_suspend()
342 r420_cp_errata_fini(rdev); in r420_suspend()
343 r100_cp_disable(rdev); in r420_suspend()
344 radeon_wb_disable(rdev); in r420_suspend()
345 r100_irq_disable(rdev); in r420_suspend()
346 if (rdev->flags & RADEON_IS_PCIE) in r420_suspend()
347 rv370_pcie_gart_disable(rdev); in r420_suspend()
348 if (rdev->flags & RADEON_IS_PCI) in r420_suspend()
349 r100_pci_gart_disable(rdev); in r420_suspend()
353 void r420_fini(struct radeon_device *rdev) in r420_fini() argument
355 radeon_pm_fini(rdev); in r420_fini()
356 r100_cp_fini(rdev); in r420_fini()
357 radeon_wb_fini(rdev); in r420_fini()
358 radeon_ib_pool_fini(rdev); in r420_fini()
359 radeon_gem_fini(rdev); in r420_fini()
360 if (rdev->flags & RADEON_IS_PCIE) in r420_fini()
361 rv370_pcie_gart_fini(rdev); in r420_fini()
362 if (rdev->flags & RADEON_IS_PCI) in r420_fini()
363 r100_pci_gart_fini(rdev); in r420_fini()
364 radeon_agp_fini(rdev); in r420_fini()
365 radeon_irq_kms_fini(rdev); in r420_fini()
366 radeon_fence_driver_fini(rdev); in r420_fini()
367 radeon_bo_fini(rdev); in r420_fini()
368 if (rdev->is_atom_bios) { in r420_fini()
369 radeon_atombios_fini(rdev); in r420_fini()
371 radeon_combios_fini(rdev); in r420_fini()
373 kfree(rdev->bios); in r420_fini()
374 rdev->bios = NULL; in r420_fini()
377 int r420_init(struct radeon_device *rdev) in r420_init() argument
382 radeon_scratch_init(rdev); in r420_init()
384 radeon_surface_init(rdev); in r420_init()
387 r100_restore_sanity(rdev); in r420_init()
389 if (!radeon_get_bios(rdev)) { in r420_init()
390 if (ASIC_IS_AVIVO(rdev)) in r420_init()
393 if (rdev->is_atom_bios) { in r420_init()
394 r = radeon_atombios_init(rdev); in r420_init()
399 r = radeon_combios_init(rdev); in r420_init()
405 if (radeon_asic_reset(rdev)) { in r420_init()
406 dev_warn(rdev->dev, in r420_init()
412 if (radeon_boot_test_post_card(rdev) == false) in r420_init()
416 radeon_get_clock_info(rdev->ddev); in r420_init()
418 if (rdev->flags & RADEON_IS_AGP) { in r420_init()
419 r = radeon_agp_init(rdev); in r420_init()
421 radeon_agp_disable(rdev); in r420_init()
425 r300_mc_init(rdev); in r420_init()
426 r420_debugfs(rdev); in r420_init()
428 radeon_fence_driver_init(rdev); in r420_init()
430 r = radeon_bo_init(rdev); in r420_init()
434 if (rdev->family == CHIP_R420) in r420_init()
435 r100_enable_bm(rdev); in r420_init()
437 if (rdev->flags & RADEON_IS_PCIE) { in r420_init()
438 r = rv370_pcie_gart_init(rdev); in r420_init()
442 if (rdev->flags & RADEON_IS_PCI) { in r420_init()
443 r = r100_pci_gart_init(rdev); in r420_init()
447 r420_set_reg_safe(rdev); in r420_init()
450 radeon_pm_init(rdev); in r420_init()
452 rdev->accel_working = true; in r420_init()
453 r = r420_startup(rdev); in r420_init()
456 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r420_init()
457 r100_cp_fini(rdev); in r420_init()
458 radeon_wb_fini(rdev); in r420_init()
459 radeon_ib_pool_fini(rdev); in r420_init()
460 radeon_irq_kms_fini(rdev); in r420_init()
461 if (rdev->flags & RADEON_IS_PCIE) in r420_init()
462 rv370_pcie_gart_fini(rdev); in r420_init()
463 if (rdev->flags & RADEON_IS_PCI) in r420_init()
464 r100_pci_gart_fini(rdev); in r420_init()
465 radeon_agp_fini(rdev); in r420_init()
466 rdev->accel_working = false; in r420_init()
477 struct radeon_device *rdev = (struct radeon_device *)m->private; in r420_debugfs_pipes_info_show() local
492 void r420_debugfs_pipes_info_init(struct radeon_device *rdev) in r420_debugfs_pipes_info_init() argument
495 struct dentry *root = rdev->ddev->primary->debugfs_root; in r420_debugfs_pipes_info_init()
497 debugfs_create_file("r420_pipes_info", 0444, root, rdev, in r420_debugfs_pipes_info_init()