44 	WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);  in radeon_overscan_setup()
45 	WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);  in radeon_overscan_setup()
46 	WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);  in radeon_overscan_setup()
384 	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;  in radeon_crtc_do_set_base()  local
544 	crtc_offset = (u32)base;  in radeon_crtc_do_set_base()
546 	WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);  in radeon_crtc_do_set_base()
554 	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);  in radeon_crtc_do_set_base()
555 	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);  in radeon_crtc_do_set_base()
556 	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);  in radeon_crtc_do_set_base()
725 	WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);  in radeon_set_crtc_timing()
726 	WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);  in radeon_set_crtc_timing()
727 	WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);  in radeon_set_crtc_timing()
728 	WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);  in radeon_set_crtc_timing()
1123 		radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;  in radeon_legacy_init_crtc()