121 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in rs600_page_flip()  local
122 	struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;  in rs600_page_flip()
123 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);  in rs600_page_flip()
128 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rs600_page_flip()
131 	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,  in rs600_page_flip()
134 	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,  in rs600_page_flip()
137 	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in rs600_page_flip()
139 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in rs600_page_flip()
144 		if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)  in rs600_page_flip()
152 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rs600_page_flip()
157 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in rs600_page_flip_pending()  local
160 	return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &  in rs600_page_flip_pending()
326 	struct radeon_crtc *radeon_crtc;  in rs600_pm_prepare()  local
331 		radeon_crtc = to_radeon_crtc(crtc);  in rs600_pm_prepare()
332 		if (radeon_crtc->enabled) {  in rs600_pm_prepare()
333 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);  in rs600_pm_prepare()
335 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in rs600_pm_prepare()
344 	struct radeon_crtc *radeon_crtc;  in rs600_pm_finish()  local
349 		radeon_crtc = to_radeon_crtc(crtc);  in rs600_pm_finish()
350 		if (radeon_crtc->enabled) {  in rs600_pm_finish()
351 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);  in rs600_pm_finish()
353 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in rs600_pm_finish()