Lines Matching refs:rdev
48 static void rv770_gpu_init(struct radeon_device *rdev);
49 void rv770_fini(struct radeon_device *rdev);
50 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
51 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
53 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
59 if (rdev->family == CHIP_RV740) in rv770_set_uvd_clocks()
60 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
73 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
93 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in rv770_set_uvd_clocks()
124 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in rv770_set_uvd_clocks()
722 static void rv770_init_golden_registers(struct radeon_device *rdev) in rv770_init_golden_registers() argument
724 switch (rdev->family) { in rv770_init_golden_registers()
726 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
729 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
732 if (rdev->pdev->device == 0x994e) in rv770_init_golden_registers()
733 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
737 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
740 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
745 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
748 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
751 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
754 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
759 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
762 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
765 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
768 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
773 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
776 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
796 u32 rv770_get_xclk(struct radeon_device *rdev) in rv770_get_xclk() argument
798 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_get_xclk()
810 void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in rv770_page_flip() argument
812 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip()
841 for (i = 0; i < rdev->usec_timeout; i++) { in rv770_page_flip()
853 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id) in rv770_page_flip_pending() argument
855 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip_pending()
863 int rv770_get_temp(struct radeon_device *rdev) in rv770_get_temp() argument
882 void rv770_pm_misc(struct radeon_device *rdev) in rv770_pm_misc() argument
884 int req_ps_idx = rdev->pm.requested_power_state_index; in rv770_pm_misc()
885 int req_cm_idx = rdev->pm.requested_clock_mode_index; in rv770_pm_misc()
886 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in rv770_pm_misc()
893 if (voltage->voltage != rdev->pm.current_vddc) { in rv770_pm_misc()
894 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in rv770_pm_misc()
895 rdev->pm.current_vddc = voltage->voltage; in rv770_pm_misc()
904 static int rv770_pcie_gart_enable(struct radeon_device *rdev) in rv770_pcie_gart_enable() argument
909 if (rdev->gart.robj == NULL) { in rv770_pcie_gart_enable()
910 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rv770_pcie_gart_enable()
913 r = radeon_gart_table_vram_pin(rdev); in rv770_pcie_gart_enable()
930 if (rdev->family == CHIP_RV740) in rv770_pcie_gart_enable()
936 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in rv770_pcie_gart_enable()
937 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in rv770_pcie_gart_enable()
938 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in rv770_pcie_gart_enable()
942 (u32)(rdev->dummy_page.addr >> 12)); in rv770_pcie_gart_enable()
946 r600_pcie_gart_tlb_flush(rdev); in rv770_pcie_gart_enable()
948 (unsigned)(rdev->mc.gtt_size >> 20), in rv770_pcie_gart_enable()
949 (unsigned long long)rdev->gart.table_addr); in rv770_pcie_gart_enable()
950 rdev->gart.ready = true; in rv770_pcie_gart_enable()
954 static void rv770_pcie_gart_disable(struct radeon_device *rdev) in rv770_pcie_gart_disable() argument
977 radeon_gart_table_vram_unpin(rdev); in rv770_pcie_gart_disable()
980 static void rv770_pcie_gart_fini(struct radeon_device *rdev) in rv770_pcie_gart_fini() argument
982 radeon_gart_fini(rdev); in rv770_pcie_gart_fini()
983 rv770_pcie_gart_disable(rdev); in rv770_pcie_gart_fini()
984 radeon_gart_table_vram_free(rdev); in rv770_pcie_gart_fini()
988 static void rv770_agp_enable(struct radeon_device *rdev) in rv770_agp_enable() argument
1015 static void rv770_mc_program(struct radeon_device *rdev) in rv770_mc_program() argument
1034 rv515_mc_stop(rdev, &save); in rv770_mc_program()
1035 if (r600_mc_wait_for_idle(rdev)) { in rv770_mc_program()
1036 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
1041 if (rdev->flags & RADEON_IS_AGP) { in rv770_mc_program()
1042 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in rv770_mc_program()
1045 rdev->mc.vram_start >> 12); in rv770_mc_program()
1047 rdev->mc.gtt_end >> 12); in rv770_mc_program()
1051 rdev->mc.gtt_start >> 12); in rv770_mc_program()
1053 rdev->mc.vram_end >> 12); in rv770_mc_program()
1057 rdev->mc.vram_start >> 12); in rv770_mc_program()
1059 rdev->mc.vram_end >> 12); in rv770_mc_program()
1061 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in rv770_mc_program()
1062 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in rv770_mc_program()
1063 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in rv770_mc_program()
1065 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in rv770_mc_program()
1068 if (rdev->flags & RADEON_IS_AGP) { in rv770_mc_program()
1069 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in rv770_mc_program()
1070 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in rv770_mc_program()
1071 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in rv770_mc_program()
1077 if (r600_mc_wait_for_idle(rdev)) { in rv770_mc_program()
1078 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
1080 rv515_mc_resume(rdev, &save); in rv770_mc_program()
1083 rv515_vga_render_disable(rdev); in rv770_mc_program()
1090 void r700_cp_stop(struct radeon_device *rdev) in r700_cp_stop() argument
1092 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r700_cp_stop()
1093 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r700_cp_stop()
1096 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r700_cp_stop()
1099 static int rv770_cp_load_microcode(struct radeon_device *rdev) in rv770_cp_load_microcode() argument
1104 if (!rdev->me_fw || !rdev->pfp_fw) in rv770_cp_load_microcode()
1107 r700_cp_stop(rdev); in rv770_cp_load_microcode()
1120 fw_data = (const __be32 *)rdev->pfp_fw->data; in rv770_cp_load_microcode()
1126 fw_data = (const __be32 *)rdev->me_fw->data; in rv770_cp_load_microcode()
1137 void r700_cp_fini(struct radeon_device *rdev) in r700_cp_fini() argument
1139 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r700_cp_fini()
1140 r700_cp_stop(rdev); in r700_cp_fini()
1141 radeon_ring_fini(rdev, ring); in r700_cp_fini()
1142 radeon_scratch_free(rdev, ring->rptr_save_reg); in r700_cp_fini()
1145 void rv770_set_clk_bypass_mode(struct radeon_device *rdev) in rv770_set_clk_bypass_mode() argument
1149 if (rdev->flags & RADEON_IS_IGP) in rv770_set_clk_bypass_mode()
1157 for (i = 0; i < rdev->usec_timeout; i++) { in rv770_set_clk_bypass_mode()
1167 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) in rv770_set_clk_bypass_mode()
1177 static void rv770_gpu_init(struct radeon_device *rdev) in rv770_gpu_init() argument
1201 rdev->config.rv770.tiling_group_size = 256; in rv770_gpu_init()
1202 switch (rdev->family) { in rv770_gpu_init()
1204 rdev->config.rv770.max_pipes = 4; in rv770_gpu_init()
1205 rdev->config.rv770.max_tile_pipes = 8; in rv770_gpu_init()
1206 rdev->config.rv770.max_simds = 10; in rv770_gpu_init()
1207 rdev->config.rv770.max_backends = 4; in rv770_gpu_init()
1208 rdev->config.rv770.max_gprs = 256; in rv770_gpu_init()
1209 rdev->config.rv770.max_threads = 248; in rv770_gpu_init()
1210 rdev->config.rv770.max_stack_entries = 512; in rv770_gpu_init()
1211 rdev->config.rv770.max_hw_contexts = 8; in rv770_gpu_init()
1212 rdev->config.rv770.max_gs_threads = 16 * 2; in rv770_gpu_init()
1213 rdev->config.rv770.sx_max_export_size = 128; in rv770_gpu_init()
1214 rdev->config.rv770.sx_max_export_pos_size = 16; in rv770_gpu_init()
1215 rdev->config.rv770.sx_max_export_smx_size = 112; in rv770_gpu_init()
1216 rdev->config.rv770.sq_num_cf_insts = 2; in rv770_gpu_init()
1218 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
1219 rdev->config.rv770.sc_prim_fifo_size = 0xF9; in rv770_gpu_init()
1220 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
1221 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
1224 rdev->config.rv770.max_pipes = 2; in rv770_gpu_init()
1225 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()
1226 rdev->config.rv770.max_simds = 8; in rv770_gpu_init()
1227 rdev->config.rv770.max_backends = 2; in rv770_gpu_init()
1228 rdev->config.rv770.max_gprs = 128; in rv770_gpu_init()
1229 rdev->config.rv770.max_threads = 248; in rv770_gpu_init()
1230 rdev->config.rv770.max_stack_entries = 256; in rv770_gpu_init()
1231 rdev->config.rv770.max_hw_contexts = 8; in rv770_gpu_init()
1232 rdev->config.rv770.max_gs_threads = 16 * 2; in rv770_gpu_init()
1233 rdev->config.rv770.sx_max_export_size = 256; in rv770_gpu_init()
1234 rdev->config.rv770.sx_max_export_pos_size = 32; in rv770_gpu_init()
1235 rdev->config.rv770.sx_max_export_smx_size = 224; in rv770_gpu_init()
1236 rdev->config.rv770.sq_num_cf_insts = 2; in rv770_gpu_init()
1238 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
1239 rdev->config.rv770.sc_prim_fifo_size = 0xf9; in rv770_gpu_init()
1240 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
1241 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
1242 if (rdev->config.rv770.sx_max_export_pos_size > 16) { in rv770_gpu_init()
1243 rdev->config.rv770.sx_max_export_pos_size -= 16; in rv770_gpu_init()
1244 rdev->config.rv770.sx_max_export_smx_size += 16; in rv770_gpu_init()
1248 rdev->config.rv770.max_pipes = 2; in rv770_gpu_init()
1249 rdev->config.rv770.max_tile_pipes = 2; in rv770_gpu_init()
1250 rdev->config.rv770.max_simds = 2; in rv770_gpu_init()
1251 rdev->config.rv770.max_backends = 1; in rv770_gpu_init()
1252 rdev->config.rv770.max_gprs = 256; in rv770_gpu_init()
1253 rdev->config.rv770.max_threads = 192; in rv770_gpu_init()
1254 rdev->config.rv770.max_stack_entries = 256; in rv770_gpu_init()
1255 rdev->config.rv770.max_hw_contexts = 4; in rv770_gpu_init()
1256 rdev->config.rv770.max_gs_threads = 8 * 2; in rv770_gpu_init()
1257 rdev->config.rv770.sx_max_export_size = 128; in rv770_gpu_init()
1258 rdev->config.rv770.sx_max_export_pos_size = 16; in rv770_gpu_init()
1259 rdev->config.rv770.sx_max_export_smx_size = 112; in rv770_gpu_init()
1260 rdev->config.rv770.sq_num_cf_insts = 1; in rv770_gpu_init()
1262 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
1263 rdev->config.rv770.sc_prim_fifo_size = 0x40; in rv770_gpu_init()
1264 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
1265 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
1268 rdev->config.rv770.max_pipes = 4; in rv770_gpu_init()
1269 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()
1270 rdev->config.rv770.max_simds = 8; in rv770_gpu_init()
1271 rdev->config.rv770.max_backends = 4; in rv770_gpu_init()
1272 rdev->config.rv770.max_gprs = 256; in rv770_gpu_init()
1273 rdev->config.rv770.max_threads = 248; in rv770_gpu_init()
1274 rdev->config.rv770.max_stack_entries = 512; in rv770_gpu_init()
1275 rdev->config.rv770.max_hw_contexts = 8; in rv770_gpu_init()
1276 rdev->config.rv770.max_gs_threads = 16 * 2; in rv770_gpu_init()
1277 rdev->config.rv770.sx_max_export_size = 256; in rv770_gpu_init()
1278 rdev->config.rv770.sx_max_export_pos_size = 32; in rv770_gpu_init()
1279 rdev->config.rv770.sx_max_export_smx_size = 224; in rv770_gpu_init()
1280 rdev->config.rv770.sq_num_cf_insts = 2; in rv770_gpu_init()
1282 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
1283 rdev->config.rv770.sc_prim_fifo_size = 0x100; in rv770_gpu_init()
1284 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
1285 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
1287 if (rdev->config.rv770.sx_max_export_pos_size > 16) { in rv770_gpu_init()
1288 rdev->config.rv770.sx_max_export_pos_size -= 16; in rv770_gpu_init()
1289 rdev->config.rv770.sx_max_export_smx_size += 16; in rv770_gpu_init()
1327 tmp = rdev->config.rv770.max_simds - in rv770_gpu_init()
1329 rdev->config.rv770.active_simds = tmp; in rv770_gpu_init()
1331 switch (rdev->config.rv770.max_tile_pipes) { in rv770_gpu_init()
1346 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; in rv770_gpu_init()
1350 for (i = 0; i < rdev->config.rv770.max_backends; i++) in rv770_gpu_init()
1354 for (i = 0; i < rdev->config.rv770.max_backends; i++) in rv770_gpu_init()
1358 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, in rv770_gpu_init()
1361 rdev->config.rv770.backend_map = tmp; in rv770_gpu_init()
1363 if (rdev->family == CHIP_RV770) in rv770_gpu_init()
1371 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); in rv770_gpu_init()
1384 rdev->config.rv770.tile_config = gb_tiling_config; in rv770_gpu_init()
1391 if (rdev->family == CHIP_RV730) { in rv770_gpu_init()
1422 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); in rv770_gpu_init()
1425 if (rdev->family != CHIP_RV740) in rv770_gpu_init()
1431 if (rdev->family != CHIP_RV770) in rv770_gpu_init()
1436 switch (rdev->family) { in rv770_gpu_init()
1449 if (rdev->family != CHIP_RV770) { in rv770_gpu_init()
1455 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1)… in rv770_gpu_init()
1456 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | in rv770_gpu_init()
1457 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); in rv770_gpu_init()
1459 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | in rv770_gpu_init()
1460 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | in rv770_gpu_init()
1461 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); in rv770_gpu_init()
1471 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | in rv770_gpu_init()
1474 switch (rdev->family) { in rv770_gpu_init()
1502 if (rdev->family == CHIP_RV710) in rv770_gpu_init()
1508 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | in rv770_gpu_init()
1509 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | in rv770_gpu_init()
1510 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); in rv770_gpu_init()
1512 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | in rv770_gpu_init()
1513 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); in rv770_gpu_init()
1515 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | in rv770_gpu_init()
1516 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | in rv770_gpu_init()
1517 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); in rv770_gpu_init()
1518 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) in rv770_gpu_init()
1519 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); in rv770_gpu_init()
1521 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); in rv770_gpu_init()
1524 …WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/… in rv770_gpu_init()
1525 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); in rv770_gpu_init()
1527 …WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/… in rv770_gpu_init()
1528 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); in rv770_gpu_init()
1530 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | in rv770_gpu_init()
1531 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | in rv770_gpu_init()
1532 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | in rv770_gpu_init()
1533 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); in rv770_gpu_init()
1547 if (rdev->family == CHIP_RV710) in rv770_gpu_init()
1554 switch (rdev->family) { in rv770_gpu_init()
1567 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; in rv770_gpu_init()
1613 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) in r700_vram_gtt_location() argument
1619 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1623 if (rdev->flags & RADEON_IS_AGP) { in r700_vram_gtt_location()
1628 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1635 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1642 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", in r700_vram_gtt_location()
1646 radeon_vram_location(rdev, &rdev->mc, 0); in r700_vram_gtt_location()
1647 rdev->mc.gtt_base_align = 0; in r700_vram_gtt_location()
1648 radeon_gtt_location(rdev, mc); in r700_vram_gtt_location()
1652 static int rv770_mc_init(struct radeon_device *rdev) in rv770_mc_init() argument
1658 rdev->mc.vram_is_ddr = true; in rv770_mc_init()
1683 rdev->mc.vram_width = numchan * chansize; in rv770_mc_init()
1685 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rv770_mc_init()
1686 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rv770_mc_init()
1688 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in rv770_mc_init()
1689 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in rv770_mc_init()
1690 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rv770_mc_init()
1691 r700_vram_gtt_location(rdev, &rdev->mc); in rv770_mc_init()
1692 radeon_update_bandwidth_info(rdev); in rv770_mc_init()
1697 static void rv770_uvd_init(struct radeon_device *rdev) in rv770_uvd_init() argument
1701 if (!rdev->has_uvd) in rv770_uvd_init()
1704 r = radeon_uvd_init(rdev); in rv770_uvd_init()
1706 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in rv770_uvd_init()
1713 rdev->has_uvd = false; in rv770_uvd_init()
1716 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in rv770_uvd_init()
1717 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in rv770_uvd_init()
1720 static void rv770_uvd_start(struct radeon_device *rdev) in rv770_uvd_start() argument
1724 if (!rdev->has_uvd) in rv770_uvd_start()
1727 r = uvd_v2_2_resume(rdev); in rv770_uvd_start()
1729 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in rv770_uvd_start()
1732 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in rv770_uvd_start()
1734 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in rv770_uvd_start()
1740 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in rv770_uvd_start()
1743 static void rv770_uvd_resume(struct radeon_device *rdev) in rv770_uvd_resume() argument
1748 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in rv770_uvd_resume()
1751 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in rv770_uvd_resume()
1752 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in rv770_uvd_resume()
1754 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in rv770_uvd_resume()
1757 r = uvd_v1_0_init(rdev); in rv770_uvd_resume()
1759 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in rv770_uvd_resume()
1764 static int rv770_startup(struct radeon_device *rdev) in rv770_startup() argument
1770 rv770_pcie_gen2_enable(rdev); in rv770_startup()
1773 r = r600_vram_scratch_init(rdev); in rv770_startup()
1777 rv770_mc_program(rdev); in rv770_startup()
1779 if (rdev->flags & RADEON_IS_AGP) { in rv770_startup()
1780 rv770_agp_enable(rdev); in rv770_startup()
1782 r = rv770_pcie_gart_enable(rdev); in rv770_startup()
1787 rv770_gpu_init(rdev); in rv770_startup()
1790 r = radeon_wb_init(rdev); in rv770_startup()
1794 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rv770_startup()
1796 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in rv770_startup()
1800 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); in rv770_startup()
1802 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in rv770_startup()
1806 rv770_uvd_start(rdev); in rv770_startup()
1809 if (!rdev->irq.installed) { in rv770_startup()
1810 r = radeon_irq_kms_init(rdev); in rv770_startup()
1815 r = r600_irq_init(rdev); in rv770_startup()
1818 radeon_irq_kms_fini(rdev); in rv770_startup()
1821 r600_irq_set(rdev); in rv770_startup()
1823 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in rv770_startup()
1824 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in rv770_startup()
1829 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in rv770_startup()
1830 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in rv770_startup()
1835 r = rv770_cp_load_microcode(rdev); in rv770_startup()
1838 r = r600_cp_resume(rdev); in rv770_startup()
1842 r = r600_dma_resume(rdev); in rv770_startup()
1846 rv770_uvd_resume(rdev); in rv770_startup()
1848 r = radeon_ib_pool_init(rdev); in rv770_startup()
1850 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in rv770_startup()
1854 r = radeon_audio_init(rdev); in rv770_startup()
1863 int rv770_resume(struct radeon_device *rdev) in rv770_resume() argument
1872 atom_asic_init(rdev->mode_info.atom_context); in rv770_resume()
1875 rv770_init_golden_registers(rdev); in rv770_resume()
1877 if (rdev->pm.pm_method == PM_METHOD_DPM) in rv770_resume()
1878 radeon_pm_resume(rdev); in rv770_resume()
1880 rdev->accel_working = true; in rv770_resume()
1881 r = rv770_startup(rdev); in rv770_resume()
1884 rdev->accel_working = false; in rv770_resume()
1892 int rv770_suspend(struct radeon_device *rdev) in rv770_suspend() argument
1894 radeon_pm_suspend(rdev); in rv770_suspend()
1895 radeon_audio_fini(rdev); in rv770_suspend()
1896 if (rdev->has_uvd) { in rv770_suspend()
1897 uvd_v1_0_fini(rdev); in rv770_suspend()
1898 radeon_uvd_suspend(rdev); in rv770_suspend()
1900 r700_cp_stop(rdev); in rv770_suspend()
1901 r600_dma_stop(rdev); in rv770_suspend()
1902 r600_irq_suspend(rdev); in rv770_suspend()
1903 radeon_wb_disable(rdev); in rv770_suspend()
1904 rv770_pcie_gart_disable(rdev); in rv770_suspend()
1915 int rv770_init(struct radeon_device *rdev) in rv770_init() argument
1920 if (!radeon_get_bios(rdev)) { in rv770_init()
1921 if (ASIC_IS_AVIVO(rdev)) in rv770_init()
1925 if (!rdev->is_atom_bios) { in rv770_init()
1926 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); in rv770_init()
1929 r = radeon_atombios_init(rdev); in rv770_init()
1933 if (!radeon_card_posted(rdev)) { in rv770_init()
1934 if (!rdev->bios) { in rv770_init()
1935 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in rv770_init()
1939 atom_asic_init(rdev->mode_info.atom_context); in rv770_init()
1942 rv770_init_golden_registers(rdev); in rv770_init()
1944 r600_scratch_init(rdev); in rv770_init()
1946 radeon_surface_init(rdev); in rv770_init()
1948 radeon_get_clock_info(rdev->ddev); in rv770_init()
1950 radeon_fence_driver_init(rdev); in rv770_init()
1952 if (rdev->flags & RADEON_IS_AGP) { in rv770_init()
1953 r = radeon_agp_init(rdev); in rv770_init()
1955 radeon_agp_disable(rdev); in rv770_init()
1957 r = rv770_mc_init(rdev); in rv770_init()
1961 r = radeon_bo_init(rdev); in rv770_init()
1965 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in rv770_init()
1966 r = r600_init_microcode(rdev); in rv770_init()
1974 radeon_pm_init(rdev); in rv770_init()
1976 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in rv770_init()
1977 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in rv770_init()
1979 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; in rv770_init()
1980 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); in rv770_init()
1982 rv770_uvd_init(rdev); in rv770_init()
1984 rdev->ih.ring_obj = NULL; in rv770_init()
1985 r600_ih_ring_init(rdev, 64 * 1024); in rv770_init()
1987 r = r600_pcie_gart_init(rdev); in rv770_init()
1991 rdev->accel_working = true; in rv770_init()
1992 r = rv770_startup(rdev); in rv770_init()
1994 dev_err(rdev->dev, "disabling GPU acceleration\n"); in rv770_init()
1995 r700_cp_fini(rdev); in rv770_init()
1996 r600_dma_fini(rdev); in rv770_init()
1997 r600_irq_fini(rdev); in rv770_init()
1998 radeon_wb_fini(rdev); in rv770_init()
1999 radeon_ib_pool_fini(rdev); in rv770_init()
2000 radeon_irq_kms_fini(rdev); in rv770_init()
2001 rv770_pcie_gart_fini(rdev); in rv770_init()
2002 rdev->accel_working = false; in rv770_init()
2008 void rv770_fini(struct radeon_device *rdev) in rv770_fini() argument
2010 radeon_pm_fini(rdev); in rv770_fini()
2011 r700_cp_fini(rdev); in rv770_fini()
2012 r600_dma_fini(rdev); in rv770_fini()
2013 r600_irq_fini(rdev); in rv770_fini()
2014 radeon_wb_fini(rdev); in rv770_fini()
2015 radeon_ib_pool_fini(rdev); in rv770_fini()
2016 radeon_irq_kms_fini(rdev); in rv770_fini()
2017 uvd_v1_0_fini(rdev); in rv770_fini()
2018 radeon_uvd_fini(rdev); in rv770_fini()
2019 rv770_pcie_gart_fini(rdev); in rv770_fini()
2020 r600_vram_scratch_fini(rdev); in rv770_fini()
2021 radeon_gem_fini(rdev); in rv770_fini()
2022 radeon_fence_driver_fini(rdev); in rv770_fini()
2023 radeon_agp_fini(rdev); in rv770_fini()
2024 radeon_bo_fini(rdev); in rv770_fini()
2025 radeon_atombios_fini(rdev); in rv770_fini()
2026 kfree(rdev->bios); in rv770_fini()
2027 rdev->bios = NULL; in rv770_fini()
2030 static void rv770_pcie_gen2_enable(struct radeon_device *rdev) in rv770_pcie_gen2_enable() argument
2038 if (rdev->flags & RADEON_IS_IGP) in rv770_pcie_gen2_enable()
2041 if (!(rdev->flags & RADEON_IS_PCIE)) in rv770_pcie_gen2_enable()
2045 if (ASIC_IS_X2(rdev)) in rv770_pcie_gen2_enable()
2048 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && in rv770_pcie_gen2_enable()
2049 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) in rv770_pcie_gen2_enable()