Lines Matching refs:mclk
2953 u32 mclk, sclk; in si_apply_state_adjust_rules() local
3017 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3018 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3042 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3043 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3046 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3047 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3050 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3051 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3062 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3065 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3080 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3081 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3086 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3110 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3112 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3113 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3116 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3121 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3122 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3139 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3142 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3839 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in si_get_strobe_mode_settings() argument
3845 if (mclk <= pi->mclk_strobe_mode_threshold) in si_get_strobe_mode_settings()
3849 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); in si_get_strobe_mode_settings()
3851 result = si_get_ddr3_mclk_frequency_ratio(mclk); in si_get_strobe_mode_settings()
4110 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in si_populate_mvdd_value() argument
4117 if (mclk <= pi->mvdd_split_frequency) in si_populate_mvdd_value()
4190 u16 voltage, u32 sclk, u32 mclk, in si_populate_phase_shedding_value() argument
4198 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
4285 pl->mclk); in si_populate_memory_timing_parameters()
4356 table->initialState.level.mclk.vDLL_CNTL = in si_populate_smc_initial_state()
4358 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_initial_state()
4360 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_initial_state()
4362 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_initial_state()
4364 table->initialState.level.mclk.vMPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4366 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_initial_state()
4368 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4370 table->initialState.level.mclk.vMPLL_SS = in si_populate_smc_initial_state()
4372 table->initialState.level.mclk.vMPLL_SS2 = in si_populate_smc_initial_state()
4375 table->initialState.level.mclk.mclk_value = in si_populate_smc_initial_state()
4376 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4426 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4441 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4443 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
4558 table->ACPIState.level.mclk.vDLL_CNTL = in si_populate_smc_acpi_state()
4560 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_acpi_state()
4562 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_acpi_state()
4564 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_acpi_state()
4566 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
4568 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_acpi_state()
4570 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
4572 table->ACPIState.level.mclk.vMPLL_SS = in si_populate_smc_acpi_state()
4574 table->ACPIState.level.mclk.vMPLL_SS2 = in si_populate_smc_acpi_state()
4586 table->ACPIState.level.mclk.mclk_value = 0; in si_populate_smc_acpi_state()
4857 SISLANDS_SMC_MCLK_VALUE *mclk, in si_populate_mclk_value() argument
4929 mclk->mclk_value = cpu_to_be32(memory_clock); in si_populate_mclk_value()
4930 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in si_populate_mclk_value()
4931 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); in si_populate_mclk_value()
4932 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); in si_populate_mclk_value()
4933 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in si_populate_mclk_value()
4934 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in si_populate_mclk_value()
4935 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in si_populate_mclk_value()
4936 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); in si_populate_mclk_value()
4937 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); in si_populate_mclk_value()
4938 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); in si_populate_mclk_value()
4983 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in si_convert_power_level_to_smc()
4994 if (pl->mclk > pi->mclk_edc_enable_threshold) in si_convert_power_level_to_smc()
4997 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
5000 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); in si_convert_power_level_to_smc()
5003 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= in si_convert_power_level_to_smc()
5013 pl->mclk); in si_convert_power_level_to_smc()
5020 pl->mclk, in si_convert_power_level_to_smc()
5021 &level->mclk, in si_convert_power_level_to_smc()
5054 pl->mclk, in si_convert_power_level_to_smc()
5062 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5136 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5605 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in si_convert_mc_reg_table_entry_to_smc()
6728 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_pplib_clock_info()
6729 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_pplib_clock_info()
6772 pl->mclk = rdev->clock.default_mclk; in si_parse_pplib_clock_info()
6782 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6865 u32 sclk, mclk; in si_parse_power_table() local
6871 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_power_table()
6872 mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_power_table()
6874 rdev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
7050 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7089 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7125 return pl->mclk; in si_dpm_get_current_mclk()