132 		int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);  in vc4_v3d_pm_get()
150 		pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);  in vc4_v3d_pm_put()
151 		pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev);  in vc4_v3d_pm_put()
230 	struct vc4_v3d *v3d = vc4->v3d;  in bin_bo_alloc()  local
235 	if (!v3d)  in bin_bo_alloc()
253 			dev_err(&v3d->pdev->dev,  in bin_bo_alloc()
359 	struct vc4_v3d *v3d = dev_get_drvdata(dev);  in vc4_v3d_runtime_suspend()  local
360 	struct vc4_dev *vc4 = v3d->vc4;  in vc4_v3d_runtime_suspend()
364 	clk_disable_unprepare(v3d->clk);  in vc4_v3d_runtime_suspend()
371 	struct vc4_v3d *v3d = dev_get_drvdata(dev);  in vc4_v3d_runtime_resume()  local
372 	struct vc4_dev *vc4 = v3d->vc4;  in vc4_v3d_runtime_resume()
375 	ret = clk_prepare_enable(v3d->clk);  in vc4_v3d_runtime_resume()
394 	struct vc4_v3d *v3d = NULL;  in vc4_v3d_bind()  local
397 	v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL);  in vc4_v3d_bind()
398 	if (!v3d)  in vc4_v3d_bind()
401 	dev_set_drvdata(dev, v3d);  in vc4_v3d_bind()
403 	v3d->pdev = pdev;  in vc4_v3d_bind()
405 	v3d->regs = vc4_ioremap_regs(pdev, 0);  in vc4_v3d_bind()
406 	if (IS_ERR(v3d->regs))  in vc4_v3d_bind()
407 		return PTR_ERR(v3d->regs);  in vc4_v3d_bind()
408 	v3d->regset.base = v3d->regs;  in vc4_v3d_bind()
409 	v3d->regset.regs = v3d_regs;  in vc4_v3d_bind()
410 	v3d->regset.nregs = ARRAY_SIZE(v3d_regs);  in vc4_v3d_bind()
412 	vc4->v3d = v3d;  in vc4_v3d_bind()
413 	v3d->vc4 = vc4;  in vc4_v3d_bind()
415 	v3d->clk = devm_clk_get(dev, NULL);  in vc4_v3d_bind()
416 	if (IS_ERR(v3d->clk)) {  in vc4_v3d_bind()
417 		int ret = PTR_ERR(v3d->clk);  in vc4_v3d_bind()
422 			v3d->clk = NULL;  in vc4_v3d_bind()
437 	ret = clk_prepare_enable(v3d->clk);  in vc4_v3d_bind()
466 	vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset);  in vc4_v3d_bind()
488 	vc4->v3d = NULL;  in vc4_v3d_unbind()