1364 	hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);  in read_write_csr()
1467 	hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);  in dc_access_lcb_cntr()
1517 	hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);  in read_write_sw()
12204 			hfi1_cdbg(CNTR, "reading %s", entry->name);  in hfi1_read_cntrs()
12207 				hfi1_cdbg(CNTR, "\tDisabled\n");  in hfi1_read_cntrs()
12210 					hfi1_cdbg(CNTR, "\tPer VL\n");  in hfi1_read_cntrs()
12217 						   CNTR,  in hfi1_read_cntrs()
12224 					hfi1_cdbg(CNTR,  in hfi1_read_cntrs()
12231 						hfi1_cdbg(CNTR,  in hfi1_read_cntrs()
12242 					hfi1_cdbg(CNTR, "\tRead 0x%llx", val);  in hfi1_read_cntrs()
12270 			hfi1_cdbg(CNTR, "reading %s", entry->name);  in hfi1_read_portcntrs()
12273 				hfi1_cdbg(CNTR, "\tDisabled\n");  in hfi1_read_portcntrs()
12278 				hfi1_cdbg(CNTR, "\tPer VL");  in hfi1_read_portcntrs()
12284 					   CNTR,  in hfi1_read_portcntrs()
12295 				hfi1_cdbg(CNTR, "\tRead 0x%llx", val);  in hfi1_read_portcntrs()
12348 	hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);  in read_dev_port_cntr()
12383 	hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);  in read_dev_port_cntr()
12399 	hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);  in write_dev_port_cntr()
12417 	hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);  in write_dev_port_cntr()
12515 	    CNTR,  in do_update_synth_timer()
12525 		hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",  in do_update_synth_timer()
12529 		hfi1_cdbg(CNTR,  in do_update_synth_timer()
12533 			hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",  in do_update_synth_timer()
12540 		hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);  in do_update_synth_timer()
12577 		hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",  in do_update_synth_timer()
12581 		hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);  in do_update_synth_timer()