56 	struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);  in fpga_irq_mask()  local
59 	writel(mask, f->base + IRQ_ENABLE_CLEAR);  in fpga_irq_mask()
64 	struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);  in fpga_irq_unmask()  local
67 	writel(mask, f->base + IRQ_ENABLE_SET);  in fpga_irq_unmask()
73 	struct fpga_irq_data *f = irq_desc_get_handler_data(desc);  in fpga_irq_handle()  local
78 	status = readl(f->base + IRQ_STATUS);  in fpga_irq_handle()
88 		generic_handle_domain_irq(f->domain, irq);  in fpga_irq_handle()
100 static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)  in handle_one_fpga()  argument
106 	while ((status  = readl(f->base + IRQ_STATUS))) {  in handle_one_fpga()
108 		handle_domain_irq(f->domain, irq, regs);  in handle_one_fpga()
132 	struct fpga_irq_data *f = d->host_data;  in fpga_irqdomain_map()  local
135 	if (!(f->valid & BIT(hwirq)))  in fpga_irqdomain_map()
137 	irq_set_chip_data(irq, f);  in fpga_irqdomain_map()
138 	irq_set_chip_and_handler(irq, &f->chip,  in fpga_irqdomain_map()
152 	struct fpga_irq_data *f;  in fpga_irq_init()  local
159 	f = &fpga_irq_devices[fpga_irq_id];  in fpga_irq_init()
160 	f->base = base;  in fpga_irq_init()
161 	f->chip.name = name;  in fpga_irq_init()
162 	f->chip.irq_ack = fpga_irq_mask;  in fpga_irq_init()
163 	f->chip.irq_mask = fpga_irq_mask;  in fpga_irq_init()
164 	f->chip.irq_unmask = fpga_irq_unmask;  in fpga_irq_init()
165 	f->valid = valid;  in fpga_irq_init()
169 						 f);  in fpga_irq_init()
173 	f->domain = irq_domain_add_simple(node, fls(valid), irq_start,  in fpga_irq_init()
174 					  &fpga_irqdomain_ops, f);  in fpga_irq_init()
180 				irq_create_mapping(f->domain, i);  in fpga_irq_init()
181 			f->used_irqs++;  in fpga_irq_init()
185 		fpga_irq_id, name, base, f->used_irqs);  in fpga_irq_init()