Lines Matching refs:status
317 int status = 0; in WriteTable() local
322 while (!status) { in WriteTable()
335 status = WriteBlock(state, Address, Length * 2, pTable, 0); in WriteTable()
338 return status; in WriteTable()
357 int status; in InitCE() local
361 status = WriteTable(state, state->m_InitCE); in InitCE()
362 if (status < 0) in InitCE()
370 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); in InitCE()
371 if (status < 0) in InitCE()
374 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); in InitCE()
375 if (status < 0) in InitCE()
378 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); in InitCE()
379 if (status < 0) in InitCE()
382 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); in InitCE()
383 if (status < 0) in InitCE()
388 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); in InitCE()
389 if (status < 0) in InitCE()
392 return status; in InitCE()
397 int status = 0; in StopOC() local
405 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); in StopOC()
406 if (status < 0) in StopOC()
413 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); in StopOC()
414 if (status < 0) in StopOC()
416 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); in StopOC()
417 if (status < 0) in StopOC()
419 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); in StopOC()
420 if (status < 0) in StopOC()
422 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); in StopOC()
423 if (status < 0) in StopOC()
427 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
428 if (status < 0) in StopOC()
430 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StopOC()
431 if (status < 0) in StopOC()
436 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); in StopOC()
437 if (status < 0) in StopOC()
442 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); in StopOC()
443 if (status < 0) in StopOC()
448 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
449 if (status < 0) in StopOC()
451 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); in StopOC()
452 if (status < 0) in StopOC()
454 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StopOC()
455 if (status < 0) in StopOC()
459 return status; in StopOC()
464 int status = 0; in StartOC() local
468 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StartOC()
469 if (status < 0) in StartOC()
473 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
474 if (status < 0) in StartOC()
476 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
477 if (status < 0) in StartOC()
481 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); in StartOC()
482 if (status < 0) in StartOC()
486 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StartOC()
487 if (status < 0) in StartOC()
490 return status; in StartOC()
525 int status; in DRX_GetLockStatus() local
529 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); in DRX_GetLockStatus()
530 if (status < 0) { in DRX_GetLockStatus()
531 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); in DRX_GetLockStatus()
532 return status; in DRX_GetLockStatus()
555 int status; in SetCfgIfAgc() local
565 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
566 if (status < 0) in SetCfgIfAgc()
570 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
571 if (status < 0) in SetCfgIfAgc()
576 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); in SetCfgIfAgc()
577 if (status < 0) in SetCfgIfAgc()
594 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
595 if (status < 0) in SetCfgIfAgc()
600 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
601 if (status < 0) in SetCfgIfAgc()
608 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); in SetCfgIfAgc()
609 if (status < 0) in SetCfgIfAgc()
619 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); in SetCfgIfAgc()
620 if (status < 0) in SetCfgIfAgc()
622 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); in SetCfgIfAgc()
623 if (status < 0) in SetCfgIfAgc()
672 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); in SetCfgIfAgc()
673 if (status < 0) in SetCfgIfAgc()
675 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); in SetCfgIfAgc()
676 if (status < 0) in SetCfgIfAgc()
678 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); in SetCfgIfAgc()
679 if (status < 0) in SetCfgIfAgc()
681 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); in SetCfgIfAgc()
682 if (status < 0) in SetCfgIfAgc()
684 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); in SetCfgIfAgc()
685 if (status < 0) in SetCfgIfAgc()
695 return status; in SetCfgIfAgc()
700 int status = 0; in SetCfgRfAgc() local
713 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); in SetCfgRfAgc()
714 if (status < 0) in SetCfgRfAgc()
723 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
724 if (status < 0) in SetCfgRfAgc()
727 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
728 if (status < 0) in SetCfgRfAgc()
734 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
735 if (status < 0) in SetCfgRfAgc()
741 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
742 if (status < 0) in SetCfgRfAgc()
748 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
749 if (status < 0) in SetCfgRfAgc()
765 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
766 if (status < 0) in SetCfgRfAgc()
769 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
770 if (status < 0) in SetCfgRfAgc()
776 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
777 if (status < 0) in SetCfgRfAgc()
782 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); in SetCfgRfAgc()
783 if (status < 0) in SetCfgRfAgc()
793 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
794 if (status < 0) in SetCfgRfAgc()
800 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
801 if (status < 0) in SetCfgRfAgc()
816 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
817 if (status < 0) in SetCfgRfAgc()
820 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
821 if (status < 0) in SetCfgRfAgc()
827 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
828 if (status < 0) in SetCfgRfAgc()
834 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
835 if (status < 0) in SetCfgRfAgc()
841 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
842 if (status < 0) in SetCfgRfAgc()
847 return status; in SetCfgRfAgc()
852 int status = 0; in ReadIFAgc() local
857 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); in ReadIFAgc()
859 if (status >= 0) { in ReadIFAgc()
887 return status; in ReadIFAgc()
918 int i, status = 0; in DownloadMicrocode() local
949 status = WriteBlock(state, Address, BlockSize, in DownloadMicrocode()
951 if (status < 0) in DownloadMicrocode()
957 return status; in DownloadMicrocode()
963 int status; in HI_Command() local
965 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); in HI_Command()
966 if (status < 0) in HI_Command()
967 return status; in HI_Command()
972 status = -1; in HI_Command()
975 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0); in HI_Command()
976 } while (status != 0); in HI_Command()
978 if (status >= 0) in HI_Command()
979 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); in HI_Command()
980 return status; in HI_Command()
985 int status = 0; in HI_CfgCommand() local
998 status = Write16(state, HI_RA_RAM_SRV_CMD__A, in HI_CfgCommand()
1001 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); in HI_CfgCommand()
1003 return status; in HI_CfgCommand()
1016 int status; in HI_ResetCommand() local
1019 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, in HI_ResetCommand()
1021 if (status == 0) in HI_ResetCommand()
1022 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); in HI_ResetCommand()
1025 return status; in HI_ResetCommand()
1048 int status;
1060 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1061 if (status < 0)
1063 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1064 if (status < 0)
1066 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1067 if (status < 0)
1069 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1070 if (status < 0)
1072 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1073 if (status < 0)
1076 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1077 if (status < 0)
1082 if (status >= 0) {
1086 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1088 if (status < 0)
1095 return status;
1102 int status;
1106 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1110 return status;
1135 int status = 0; in InitCC() local
1144 status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); in InitCC()
1145 status |= Write16(state, CC_REG_PLL_MODE__A, in InitCC()
1148 status |= Write16(state, CC_REG_REF_DIVIDE__A, in InitCC()
1150 status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, in InitCC()
1152 status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); in InitCC()
1154 return status; in InitCC()
1159 int status = 0; in ResetECOD() local
1162 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1164 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1166 if (!(status < 0)) in ResetECOD()
1167 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1168 if (!(status < 0)) in ResetECOD()
1169 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); in ResetECOD()
1170 return status; in ResetECOD()
1177 int status; in SetCfgPga() local
1184 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1185 if (status < 0) in SetCfgPga()
1189 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1190 if (status < 0) in SetCfgPga()
1194 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1195 if (status < 0) in SetCfgPga()
1199 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1200 if (status < 0) in SetCfgPga()
1205 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x000… in SetCfgPga()
1206 if (status < 0) in SetCfgPga()
1212 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1213 if (status < 0) in SetCfgPga()
1217 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1218 if (status < 0) in SetCfgPga()
1222 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1223 if (status < 0) in SetCfgPga()
1227 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1228 if (status < 0) in SetCfgPga()
1233 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x000… in SetCfgPga()
1234 if (status < 0) in SetCfgPga()
1238 return status; in SetCfgPga()
1243 int status; in InitFE() local
1246 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1247 if (status < 0) in InitFE()
1251 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1256 status = SetCfgPga(state, 0); in InitFE()
1258 status = in InitFE()
1264 if (status < 0) in InitFE()
1266 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1267 if (status < 0) in InitFE()
1269 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1270 if (status < 0) in InitFE()
1273 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1274 if (status < 0) in InitFE()
1279 return status; in InitFE()
1296 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0); in SC_WaitForReady() local
1297 if (status == 0) in SC_WaitForReady()
1298 return status; in SC_WaitForReady()
1305 int status = 0, ret; in SC_SendCommand() local
1308 status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0); in SC_SendCommand()
1309 if (status < 0) in SC_SendCommand()
1310 return status; in SC_SendCommand()
1318 status = -1; in SC_SendCommand()
1321 return status; in SC_SendCommand()
1327 int ret, status = 0; in SC_ProcStartCommand() local
1334 status = -1; in SC_ProcStartCommand()
1338 status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_ProcStartCommand()
1339 status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_ProcStartCommand()
1340 status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_ProcStartCommand()
1345 return status; in SC_ProcStartCommand()
1351 int status; in SC_SetPrefParamCommand() local
1355 status = SC_WaitForReady(state); in SC_SetPrefParamCommand()
1356 if (status < 0) in SC_SetPrefParamCommand()
1358 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_SetPrefParamCommand()
1359 if (status < 0) in SC_SetPrefParamCommand()
1361 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_SetPrefParamCommand()
1362 if (status < 0) in SC_SetPrefParamCommand()
1364 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_SetPrefParamCommand()
1365 if (status < 0) in SC_SetPrefParamCommand()
1368 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); in SC_SetPrefParamCommand()
1369 if (status < 0) in SC_SetPrefParamCommand()
1373 return status; in SC_SetPrefParamCommand()
1379 int status = 0;
1383 status = SC_WaitForReady(state);
1384 if (status < 0)
1386 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1387 if (status < 0)
1389 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1390 if (status < 0)
1394 return status;
1400 int status; in ConfigureMPEGOutput() local
1472 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); in ConfigureMPEGOutput()
1473 if (status < 0) in ConfigureMPEGOutput()
1475 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); in ConfigureMPEGOutput()
1476 if (status < 0) in ConfigureMPEGOutput()
1478 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); in ConfigureMPEGOutput()
1479 if (status < 0) in ConfigureMPEGOutput()
1481 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); in ConfigureMPEGOutput()
1482 if (status < 0) in ConfigureMPEGOutput()
1485 return status; in ConfigureMPEGOutput()
1490 int status = 0; in SetDeviceTypeId() local
1494 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1495 if (status < 0) in SetDeviceTypeId()
1498 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1499 if (status < 0) in SetDeviceTypeId()
1527 status = -1; in SetDeviceTypeId()
1533 if (status < 0) in SetDeviceTypeId()
1534 return status; in SetDeviceTypeId()
1579 return status; in SetDeviceTypeId()
1584 int status; in CorrectSysClockDeviation() local
1598 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); in CorrectSysClockDeviation()
1599 if (status < 0) in CorrectSysClockDeviation()
1601 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); in CorrectSysClockDeviation()
1602 if (status < 0) in CorrectSysClockDeviation()
1658 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); in CorrectSysClockDeviation()
1659 if (status < 0) in CorrectSysClockDeviation()
1663 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1664 if (status < 0) in CorrectSysClockDeviation()
1670 return status; in CorrectSysClockDeviation()
1675 int status; in DRX_Stop() local
1683 status = DRX_GetLockStatus(state, &lock); in DRX_Stop()
1684 if (status < 0) in DRX_Stop()
1688 status = StopOC(state); in DRX_Stop()
1689 if (status < 0) in DRX_Stop()
1694 status = ConfigureMPEGOutput(state, 0); in DRX_Stop()
1695 if (status < 0) in DRX_Stop()
1700 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); in DRX_Stop()
1701 if (status < 0) in DRX_Stop()
1704 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1705 if (status < 0) in DRX_Stop()
1707 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1708 if (status < 0) in DRX_Stop()
1712 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1713 if (status < 0) in DRX_Stop()
1715 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1716 if (status < 0) in DRX_Stop()
1718 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1719 if (status < 0) in DRX_Stop()
1721 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1722 if (status < 0) in DRX_Stop()
1724 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1725 if (status < 0) in DRX_Stop()
1727 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1728 if (status < 0) in DRX_Stop()
1730 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); in DRX_Stop()
1731 if (status < 0) in DRX_Stop()
1736 return status; in DRX_Stop()
1742 int status;
1746 status = -1;
1751 status = 0;
1756 status = -1;
1762 status = WriteTable(state, state->m_InitDiversityFront);
1765 status = WriteTable(state, state->m_InitDiversityEnd);
1771 status = WriteTable(state, state->m_DisableDiversity);
1776 if (!status)
1778 return status;
1784 int status = 0; in StartDiversity() local
1789 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1790 if (status < 0) in StartDiversity()
1793 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1794 if (status < 0) in StartDiversity()
1797 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1798 if (status < 0) in StartDiversity()
1801 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1802 if (status < 0) in StartDiversity()
1806 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); in StartDiversity()
1807 if (status < 0) in StartDiversity()
1815 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); in StartDiversity()
1816 if (status < 0) in StartDiversity()
1820 return status; in StartDiversity()
1865 int status = 0; in SetCfgNoiseCalibration() local
1868 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); in SetCfgNoiseCalibration()
1869 if (status < 0) in SetCfgNoiseCalibration()
1875 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1876 if (status < 0) in SetCfgNoiseCalibration()
1879 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); in SetCfgNoiseCalibration()
1880 if (status < 0) in SetCfgNoiseCalibration()
1884 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1885 if (status < 0) in SetCfgNoiseCalibration()
1887 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1888 if (status < 0) in SetCfgNoiseCalibration()
1893 return status; in SetCfgNoiseCalibration()
1899 int status; in DRX_Start() local
1929 status = ResetECOD(state); in DRX_Start()
1930 if (status < 0) in DRX_Start()
1933 status = InitSC(state); in DRX_Start()
1934 if (status < 0) in DRX_Start()
1937 status = InitFT(state); in DRX_Start()
1938 if (status < 0) in DRX_Start()
1940 status = InitCP(state); in DRX_Start()
1941 if (status < 0) in DRX_Start()
1943 status = InitCE(state); in DRX_Start()
1944 if (status < 0) in DRX_Start()
1946 status = InitEQ(state); in DRX_Start()
1947 if (status < 0) in DRX_Start()
1949 status = InitSC(state); in DRX_Start()
1950 if (status < 0) in DRX_Start()
1956 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1957 if (status < 0) in DRX_Start()
1959 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1960 if (status < 0) in DRX_Start()
1972 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); in DRX_Start()
1973 if (status < 0) in DRX_Start()
1983 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); in DRX_Start()
1984 if (status < 0) in DRX_Start()
2017 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2018 if (status < 0) in DRX_Start()
2020 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2021 if (status < 0) in DRX_Start()
2047 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2048 if (status < 0) in DRX_Start()
2050 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2051 if (status < 0) in DRX_Start()
2076 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2077 if (status < 0) in DRX_Start()
2079 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2080 if (status < 0) in DRX_Start()
2108 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2109 if (status < 0) in DRX_Start()
2111 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2112 if (status < 0) in DRX_Start()
2135 if (status < 0) in DRX_Start()
2145 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); in DRX_Start()
2146 if (status < 0) in DRX_Start()
2148 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); in DRX_Start()
2149 if (status < 0) in DRX_Start()
2151 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); in DRX_Start()
2152 if (status < 0) in DRX_Start()
2154 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); in DRX_Start()
2155 if (status < 0) in DRX_Start()
2157 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); in DRX_Start()
2158 if (status < 0) in DRX_Start()
2161 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); in DRX_Start()
2162 if (status < 0) in DRX_Start()
2164 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); in DRX_Start()
2165 if (status < 0) in DRX_Start()
2167 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); in DRX_Start()
2168 if (status < 0) in DRX_Start()
2170 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); in DRX_Start()
2171 if (status < 0) in DRX_Start()
2178 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); in DRX_Start()
2179 if (status < 0) in DRX_Start()
2181 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); in DRX_Start()
2182 if (status < 0) in DRX_Start()
2184 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2185 if (status < 0) in DRX_Start()
2187 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); in DRX_Start()
2188 if (status < 0) in DRX_Start()
2190 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2191 if (status < 0) in DRX_Start()
2194 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); in DRX_Start()
2195 if (status < 0) in DRX_Start()
2197 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); in DRX_Start()
2198 if (status < 0) in DRX_Start()
2200 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); in DRX_Start()
2201 if (status < 0) in DRX_Start()
2203 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); in DRX_Start()
2204 if (status < 0) in DRX_Start()
2212 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); in DRX_Start()
2213 if (status < 0) in DRX_Start()
2215 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); in DRX_Start()
2216 if (status < 0) in DRX_Start()
2218 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2219 if (status < 0) in DRX_Start()
2221 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); in DRX_Start()
2222 if (status < 0) in DRX_Start()
2224 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2225 if (status < 0) in DRX_Start()
2228 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); in DRX_Start()
2229 if (status < 0) in DRX_Start()
2231 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); in DRX_Start()
2232 if (status < 0) in DRX_Start()
2234 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); in DRX_Start()
2235 if (status < 0) in DRX_Start()
2237 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); in DRX_Start()
2238 if (status < 0) in DRX_Start()
2244 if (status < 0) in DRX_Start()
2252 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); in DRX_Start()
2256 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); in DRX_Start()
2264 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); in DRX_Start()
2272 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); in DRX_Start()
2277 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); in DRX_Start()
2282 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); in DRX_Start()
2287 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); in DRX_Start()
2290 if (status < 0) in DRX_Start()
2309 status = Write16(state, in DRX_Start()
2316 status = Write16(state, in DRX_Start()
2323 status = Write16(state, in DRX_Start()
2327 status = -EINVAL; in DRX_Start()
2329 if (status < 0) in DRX_Start()
2332 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); in DRX_Start()
2333 if (status < 0) in DRX_Start()
2338 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); in DRX_Start()
2339 if (status < 0) in DRX_Start()
2352 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); in DRX_Start()
2353 if (status < 0) in DRX_Start()
2357 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2358 if (status < 0) in DRX_Start()
2363 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); in DRX_Start()
2364 if (status < 0) in DRX_Start()
2375 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); in DRX_Start()
2376 if (status < 0) in DRX_Start()
2378 …status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_IN… in DRX_Start()
2379 if (status < 0) in DRX_Start()
2389 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); in DRX_Start()
2390 if (status < 0) in DRX_Start()
2392 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); in DRX_Start()
2393 if (status < 0) in DRX_Start()
2404 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); in DRX_Start()
2405 if (status < 0) in DRX_Start()
2409 …status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_… in DRX_Start()
2410 if (status < 0) in DRX_Start()
2413 status = StartOC(state); in DRX_Start()
2414 if (status < 0) in DRX_Start()
2418 status = StartDiversity(state); in DRX_Start()
2419 if (status < 0) in DRX_Start()
2426 return status; in DRX_Start()
2584 int status = 0; in DRXD_init() local
2595 status = SetDeviceTypeId(state); in DRXD_init()
2596 if (status < 0) in DRXD_init()
2601 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2602 if (status < 0) in DRXD_init()
2609 status = Write16(state, 0x43012D, 0x047f, 0); in DRXD_init()
2610 if (status < 0) in DRXD_init()
2614 status = HI_ResetCommand(state); in DRXD_init()
2615 if (status < 0) in DRXD_init()
2618 status = StopAllProcessors(state); in DRXD_init()
2619 if (status < 0) in DRXD_init()
2621 status = InitCC(state); in DRXD_init()
2622 if (status < 0) in DRXD_init()
2651 status = InitHI(state); in DRXD_init()
2652 if (status < 0) in DRXD_init()
2654 status = InitAtomicRead(state); in DRXD_init()
2655 if (status < 0) in DRXD_init()
2658 status = EnableAndResetMB(state); in DRXD_init()
2659 if (status < 0) in DRXD_init()
2662 status = ResetCEFR(state); in DRXD_init()
2663 if (status < 0) in DRXD_init()
2667 status = DownloadMicrocode(state, fw, fw_size); in DRXD_init()
2668 if (status < 0) in DRXD_init()
2671 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2672 if (status < 0) in DRXD_init()
2685 status = InitFE(state); in DRXD_init()
2686 if (status < 0) in DRXD_init()
2688 status = InitFT(state); in DRXD_init()
2689 if (status < 0) in DRXD_init()
2691 status = InitCP(state); in DRXD_init()
2692 if (status < 0) in DRXD_init()
2694 status = InitCE(state); in DRXD_init()
2695 if (status < 0) in DRXD_init()
2697 status = InitEQ(state); in DRXD_init()
2698 if (status < 0) in DRXD_init()
2700 status = InitEC(state); in DRXD_init()
2701 if (status < 0) in DRXD_init()
2703 status = InitSC(state); in DRXD_init()
2704 if (status < 0) in DRXD_init()
2707 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2708 if (status < 0) in DRXD_init()
2710 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2711 if (status < 0) in DRXD_init()
2715 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2716 if (status < 0) in DRXD_init()
2718 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2719 if (status < 0) in DRXD_init()
2730 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); in DRXD_init()
2731 if (status < 0) in DRXD_init()
2734 status = StopOC(state); in DRXD_init()
2735 if (status < 0) in DRXD_init()
2740 status = 0; in DRXD_init()
2742 return status; in DRXD_init()
2777 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status) in drxd_read_status() argument
2783 *status = 0; in drxd_read_status()
2787 *status |= FE_HAS_LOCK; in drxd_read_status()
2790 *status |= FE_HAS_LOCK; in drxd_read_status()
2793 *status |= FE_HAS_VITERBI | FE_HAS_SYNC; in drxd_read_status()
2795 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; in drxd_read_status()