101 	mfc_write(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);  in s5p_mfc_bus_reset()
125 		mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);  in s5p_mfc_reset()
126 		mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);  in s5p_mfc_reset()
127 		mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);  in s5p_mfc_reset()
130 			mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));  in s5p_mfc_reset()
141 			mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);  in s5p_mfc_reset()
143 		mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);  in s5p_mfc_reset()
144 		mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);  in s5p_mfc_reset()
148 		mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);  in s5p_mfc_reset()
150 		mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);  in s5p_mfc_reset()
165 		mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);  in s5p_mfc_reset()
166 		mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);  in s5p_mfc_reset()
176 		mfc_write(dev, dev->dma_base[BANK_L_CTX],  in s5p_mfc_init_memctrl()
181 		mfc_write(dev, dev->dma_base[BANK_L_CTX],  in s5p_mfc_init_memctrl()
183 		mfc_write(dev, dev->dma_base[BANK_R_CTX],  in s5p_mfc_init_memctrl()
197 		mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);  in s5p_mfc_clear_cmds()
198 		mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);  in s5p_mfc_clear_cmds()
199 		mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);  in s5p_mfc_clear_cmds()
200 		mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);  in s5p_mfc_clear_cmds()
234 		mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);  in s5p_mfc_init_hw()
237 		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);  in s5p_mfc_init_hw()
240 		mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);  in s5p_mfc_init_hw()
334 	mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);  in s5p_mfc_v8_wait_wakeup()
368 		mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);  in s5p_mfc_wait_wakeup()
370 		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);  in s5p_mfc_wait_wakeup()