Lines Matching refs:mclk
391 unsigned long mclk; member
407 unsigned long mclk, in sm501_calc_clock() argument
422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq; in sm501_calc_clock()
430 clock->mclk = mclk; in sm501_calc_clock()
452 unsigned long mclk; in sm501_calc_pll() local
463 mclk = (24000000UL * m / n) >> k; in sm501_calc_pll()
466 mclk, &best_diff)) { in sm501_calc_pll()
476 return clock->mclk / (clock->divider << clock->shift); in sm501_calc_pll()
490 unsigned long mclk; in sm501_select_clock() local
494 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { in sm501_select_clock()
495 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff); in sm501_select_clock()
499 return clock->mclk / (clock->divider << clock->shift); in sm501_select_clock()
551 if (to.mclk != 288000000) in sm501_set_clock()
564 if (to.mclk != 288000000) in sm501_set_clock()
576 if (to.mclk != 288000000) in sm501_set_clock()
1259 if (init->mclk) { in sm501_init_regs()
1260 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); in sm501_init_regs()
1261 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk); in sm501_init_regs()
1538 .mclk = 72 * MHZ,