134 	u32 addr_low, addr_high, aenq_caps;  in ena_com_admin_init_aenq()  local
151 	addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);  in ena_com_admin_init_aenq()
154 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);  in ena_com_admin_init_aenq()
1779 	u32 addr_low, addr_high;  in ena_com_mmio_reg_read_request_write_dev_addr()  local
1782 	addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);  in ena_com_mmio_reg_read_request_write_dev_addr()
1785 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);  in ena_com_mmio_reg_read_request_write_dev_addr()
1792 	u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;  in ena_com_admin_init()  local
1834 	addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);  in ena_com_admin_init()
1837 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);  in ena_com_admin_init()
1840 	addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);  in ena_com_admin_init()
1843 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);  in ena_com_admin_init()